Commit 3e5cbecb authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Use RING_PSMI_CTL rather than per-engine macros 



We have a parameterized macro for RING_PSMI_CTL; let's use that instead
of the per-engine definitions where possible.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220111051600.3429104-5-matthew.d.roper@intel.com
parent e0d47fcf

drivers/gpu/drm/i915/gt/intel_ring_submission.c

+5 −5
Original line number Diff line number Diff line
@@ -1002,15 +1002,15 @@ static void gen6_bsd_submit_request(struct i915_request *request) 
	/* Disable notification that the ring is IDLE. The GT

	 * will then assume that it is busy and bring it out of rc6.

	 */

	intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,

			      _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));

	intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),

			      _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));



	/* Clear the context id. Here be magic! */

	intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);



	/* Wait for the ring not to be idle, i.e. for it to wake up. */

	if (__intel_wait_for_register_fw(uncore,

					 GEN6_BSD_SLEEP_PSMI_CONTROL,

					 RING_PSMI_CTL(GEN6_BSD_RING_BASE),

					 GEN6_BSD_SLEEP_INDICATOR,

					 0,

					 1000, 0, NULL))
@@ -1023,8 +1023,8 @@ static void gen6_bsd_submit_request(struct i915_request *request) 
	/* Let the ring send IDLE messages to the GT again,

	 * and so let it sleep to conserve power when idle.

	 */

	intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,

			      _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));

	intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE),

			      _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));



	intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);

}

drivers/gpu/drm/i915/gt/intel_workarounds.c

+1 −1
Original line number Diff line number Diff line
@@ -1789,7 +1789,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 
		 * For DG1 this only applies to A0.

		 */

		wa_masked_en(wal,

			     GEN6_RC_SLEEP_PSMI_CONTROL,

			     RING_PSMI_CTL(RENDER_RING_BASE),

			     GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |

			     GEN8_RC_SEMA_IDLE_MSG_DISABLE);

	}

drivers/gpu/drm/i915/i915_reg.h

+7 −12
Original line number Diff line number Diff line
@@ -2296,6 +2296,13 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define GEN6_VEVSYNC	(RING_SYNC_2(VEBOX_RING_BASE))

#define GEN6_NOSYNC	INVALID_MMIO_REG

#define RING_PSMI_CTL(base)	_MMIO((base) + 0x50)

#define   GEN8_RC_SEMA_IDLE_MSG_DISABLE		REG_BIT(12)

#define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	REG_BIT(10)

#define   GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)

#define   GEN6_BSD_GO_INDICATOR			REG_BIT(4)

#define   GEN6_BSD_SLEEP_INDICATOR		REG_BIT(3)

#define   GEN6_BSD_SLEEP_FLUSH_DISABLE		REG_BIT(2)

#define   GEN6_PSMI_SLEEP_MSG_DISABLE		REG_BIT(0)

#define RING_MAX_IDLE(base)	_MMIO((base) + 0x54)

#define RING_HWS_PGA(base)	_MMIO((base) + 0x80)

#define RING_ID(base)		_MMIO((base) + 0x8c)
@@ -2841,12 +2848,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1 << 6)

#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1 << 1)



#define GEN6_RC_SLEEP_PSMI_CONTROL	_MMIO(0x2050)

#define   GEN6_PSMI_SLEEP_MSG_DISABLE	(1 << 0)

#define   GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)

#define   GEN8_RC_SEMA_IDLE_MSG_DISABLE	(1 << 12)

#define   GEN8_FF_DOP_CLOCK_GATE_DISABLE	(1 << 10)



#define GEN6_RCS_PWR_FSM _MMIO(0x22ac)

#define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
@@ -2931,12 +2932,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define XEHP_EU_ENABLE			_MMIO(0x9134)

#define XEHP_EU_ENA_MASK		0xFF



#define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)

#define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)

#define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)

#define   GEN6_BSD_SLEEP_INDICATOR	(1 << 3)

#define   GEN6_BSD_GO_INDICATOR		(1 << 4)



/* On modern GEN architectures interrupt control consists of two sets

 * of registers. The first set pertains to the ring generating the

 * interrupt. The second control is for the functional block generating the

drivers/gpu/drm/i915/intel_pm.c

+2 −2
Original line number Diff line number Diff line
@@ -7631,7 +7631,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) 
		   intel_uncore_read(&dev_priv->uncore, GEN7_FF_THREAD_MODE) &

		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));



	intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,

	intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),

		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));



	/* WaDisableSDEUnitClockGating:bdw */
@@ -7772,7 +7772,7 @@ static void chv_init_clock_gating(struct drm_i915_private *dev_priv) 
		   ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));



	/* WaDisableSemaphoreAndSyncFlipWait:chv */

	intel_uncore_write(&dev_priv->uncore, GEN6_RC_SLEEP_PSMI_CONTROL,

	intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),

		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));



	/* WaDisableCSUnitClockGating:chv */