Unverified Commit aa4890f6 authored by Shengjiu Wang's avatar Shengjiu Wang Committed by Mark Brown
Browse files

ASoC: wm8962: Relax bit clock divider searching 



With S20_3LE format case, the sysclk = rate * 384,
the bclk = rate * 20 * 2, there is no proper bclk divider
for 384 / 40, because current condition needs exact match.
So driver fails to configure the clocking:

wm8962 3-001a: Unsupported BCLK ratio 9

Fix this by relaxing bitclk divider searching, so that when
no exact value can be derived from sysclk pick the closest
value greater than expected bitclk.

Signed-off-by: default avatarShengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: default avatarDaniel Baluta <daniel.baluta@nxp.com>
Acked-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/1615170877-25918-1-git-send-email-shengjiu.wang@nxp.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 98537d5c

sound/soc/codecs/wm8962.c

+13 −10
Original line number Diff line number Diff line
@@ -2403,6 +2403,7 @@ static const int sysclk_rates[] = { 
static void wm8962_configure_bclk(struct snd_soc_component *component)

{

	struct wm8962_priv *wm8962 = snd_soc_component_get_drvdata(component);

	int best, min_diff, diff;

	int dspclk, i;

	int clocking2 = 0;

	int clocking4 = 0;
@@ -2473,23 +2474,25 @@ static void wm8962_configure_bclk(struct snd_soc_component *component) 


	dev_dbg(component->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);



	/* We're expecting an exact match */

	/* Search a proper bclk, not exact match. */

	best = 0;

	min_diff = INT_MAX;

	for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {

		if (bclk_divs[i] < 0)

			continue;



		if (dspclk / bclk_divs[i] == wm8962->bclk) {

			dev_dbg(component->dev, "Selected BCLK_DIV %d for %dHz\n",

				bclk_divs[i], wm8962->bclk);

			clocking2 |= i;

		diff = (dspclk / bclk_divs[i]) - wm8962->bclk;

		if (diff < 0) /* Table is sorted */

			break;

		if (diff < min_diff) {

			best = i;

			min_diff = diff;

		}

	}

	if (i == ARRAY_SIZE(bclk_divs)) {

		dev_err(component->dev, "Unsupported BCLK ratio %d\n",

			dspclk / wm8962->bclk);

		return;

	}

	wm8962->bclk = dspclk / bclk_divs[best];

	clocking2 |= best;

	dev_dbg(component->dev, "Selected BCLK_DIV %d for %dHz\n",

		bclk_divs[best], wm8962->bclk);



	aif2 |= wm8962->bclk / wm8962->lrclk;

	dev_dbg(component->dev, "Selected LRCLK divisor %d for %dHz\n",