Commit aa205003 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Refresh sapphirerapids events 

Update the sapphirerapids events from 1.09 to 1.11. Generation was
done using https://github.com/intel/perfmon

.

Notable changes are new events and event descriptions, TMA metrics are
updated to version 4.5, TMA info metrics are renamed from their node
name to be lower case and prefixed by tma_info_, MetricThreshold
expressions are added, smi_cost and transaction metric groups are
added replicating existing hard coded metrics in stat-shadow.

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andrii Nakryiko <andrii@kernel.org>
Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Eduard Zingerman <eddyz87@gmail.com>
Cc: Florian Fischer <florian.fischer@muhq.space>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Sean Christopherson <seanjc@google.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Suzuki Poulouse <suzuki.poulose@arm.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-stm32@st-md-mailman.stormreply.com
Link: https://lore.kernel.org/r/20230219092848.639226-27-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 4507f603

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ GenuineIntel-6-A[AC],v1.00,meteorlake,core 
GenuineIntel-6-1[AEF],v3,nehalemep,core

GenuineIntel-6-2E,v3,nehalemex,core

GenuineIntel-6-2A,v18,sandybridge,core

GenuineIntel-6-(8F|CF),v1.09,sapphirerapids,core

GenuineIntel-6-(8F|CF),v1.11,sapphirerapids,core

GenuineIntel-6-(37|4A|4C|4D|5A),v14,silvermont,core

GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core

GenuineIntel-6-55-[01234],v1.28,skylakex,core

tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json

+16 −8
Original line number Diff line number Diff line
@@ -863,6 +863,14 @@ 
        "SampleAfterValue": "1000003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.",

        "EventCode": "0x2c",

        "EventName": "SQ_MISC.BUS_LOCK",

        "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically.  Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.",

        "SampleAfterValue": "100003",

        "UMask": "0x10"

    },

    {

        "BriefDescription": "Number of PREFETCHNTA instructions executed.",

        "EventCode": "0x40",

tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json

+32 −0
Original line number Diff line number Diff line
@@ -75,6 +75,14 @@ 
        "SampleAfterValue": "100003",

        "UMask": "0x20"

    },

    {

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 or/and 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x18"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "EventCode": "0xc7",
@@ -91,6 +99,22 @@ 
        "SampleAfterValue": "100003",

        "UMask": "0x80"

    },

    {

        "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision  FP instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, 1 for each element.  Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS",

        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision  floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x60"

    },

    {

        "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below.  Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR",

        "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "1000003",

        "UMask": "0x3"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "EventCode": "0xc7",
@@ -107,6 +131,14 @@ 
        "SampleAfterValue": "100003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Number of any Vector retired FP arithmetic instructions",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.VECTOR",

        "PublicDescription": "Number of any Vector retired FP arithmetic instructions.  The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "1000003",

        "UMask": "0xfc"

    },

    {

        "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF",

        "EventCode": "0xcf",

tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json

+8 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Clears due to Unknown Branches.",

        "EventCode": "0x60",

        "EventName": "BACLEARS.ANY",

        "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Stalls caused by changing prefix length of the instruction.",

        "EventCode": "0x87",

tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json

+16 −3
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "AMX_OPS_RETIRED.BF16",

        "BriefDescription": "AMX retired arithmetic BF16 operations.",

        "EventCode": "0xce",

        "EventName": "AMX_OPS_RETIRED.BF16",

        "PublicDescription": "Number of AMX-based retired arithmetic bfloat16 (BF16) floating-point operations. Counts TDPBF16PS FP instructions. SW to use operation multiplier of 4",

        "SampleAfterValue": "1000003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "AMX_OPS_RETIRED.INT8",

        "BriefDescription": "AMX retired arithmetic integer 8-bit operations.",

        "EventCode": "0xce",

        "EventName": "AMX_OPS_RETIRED.INT8",

        "PublicDescription": "Number of AMX-based retired arithmetic integer operations of 8-bit width source operands. Counts TDPB[SS,UU,US,SU]D instructions. SW should use operation multiplier of 8.",

        "SampleAfterValue": "1000003",

        "UMask": "0x1"

    },
@@ -461,12 +463,23 @@ 
        "UMask": "0x1"

    },

    {

        "BriefDescription": "INST_RETIRED.REP_ITERATION",

        "BriefDescription": "Iterations of Repeat string retired instructions.",

        "EventCode": "0xc0",

        "EventName": "INST_RETIRED.REP_ITERATION",

        "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.",

        "SampleAfterValue": "2000003",

        "UMask": "0x8"

    },

    {

        "BriefDescription": "Clears speculative count",

        "CounterMask": "1",

        "EdgeDetect": "1",

        "EventCode": "0xad",

        "EventName": "INT_MISC.CLEARS_COUNT",

        "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears",

        "SampleAfterValue": "500009",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",

        "EventCode": "0xad",