Commit 4507f603 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Refresh sandybridge events 

Update the sandybridge events from 17 to 18. Generation was done
using https://github.com/intel/perfmon

.

Notable changes are improved event descriptions, TMA metrics are
updated to version 4.5, TMA info metrics are renamed from their node
name to be lower case and prefixed by tma_info_, MetricThreshold
expressions are added, and the smi_cost metric group is added
replicating existing hard coded metrics in stat-shadow.

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andrii Nakryiko <andrii@kernel.org>
Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Eduard Zingerman <eddyz87@gmail.com>
Cc: Florian Fischer <florian.fischer@muhq.space>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Sean Christopherson <seanjc@google.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Suzuki Poulouse <suzuki.poulose@arm.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-stm32@st-md-mailman.stormreply.com
Link: https://lore.kernel.org/r/20230219092848.639226-26-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 0a080050

tools/perf/pmu-events/arch/x86/mapfile.csv

+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ GenuineIntel-6-(57|85),v10,knightslanding,core 
GenuineIntel-6-A[AC],v1.00,meteorlake,core

GenuineIntel-6-1[AEF],v3,nehalemep,core

GenuineIntel-6-2E,v3,nehalemex,core

GenuineIntel-6-2A,v17,sandybridge,core

GenuineIntel-6-2A,v18,sandybridge,core

GenuineIntel-6-(8F|CF),v1.09,sapphirerapids,core

GenuineIntel-6-(37|4A|4C|4D|5A),v14,silvermont,core

GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core

tools/perf/pmu-events/arch/x86/sandybridge/cache.json

+4 −4
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ 
        "UMask": "0x5"

    },

    {

        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",

        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.",

        "CounterMask": "1",

        "EventCode": "0x48",

        "EventName": "L1D_PEND_MISS.FB_FULL",
@@ -45,7 +45,7 @@ 
        "UMask": "0x2"

    },

    {

        "BriefDescription": "L1D miss oustandings duration in cycles.",

        "BriefDescription": "L1D miss outstanding duration in cycles.",

        "EventCode": "0x48",

        "EventName": "L1D_PEND_MISS.PENDING",

        "SampleAfterValue": "2000003",
@@ -493,7 +493,7 @@ 
        "UMask": "0x8"

    },

    {

        "BriefDescription": "Cacheable and noncachaeble code read requests.",

        "BriefDescription": "Cacheable and noncacheable code read requests.",

        "EventCode": "0xB0",

        "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",

        "SampleAfterValue": "100003",
@@ -898,7 +898,7 @@ 
        "UMask": "0x1"

    },

    {

        "BriefDescription": "COREWB & ANY_RESPONSE",

        "BriefDescription": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",

        "EventCode": "0xB7, 0xBB",

        "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",

        "MSRIndex": "0x1a6,0x1a7",

tools/perf/pmu-events/arch/x86/sandybridge/frontend.json

+6 −6
Original line number Diff line number Diff line
@@ -134,7 +134,7 @@ 
        "UMask": "0x4"

    },

    {

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_CYCLES",
@@ -143,7 +143,7 @@ 
        "UMask": "0x30"

    },

    {

        "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",

        "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_DSB_CYCLES",
@@ -151,7 +151,7 @@ 
        "UMask": "0x10"

    },

    {

        "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",

        "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",

        "CounterMask": "1",

        "EdgeDetect": "1",

        "EventCode": "0x79",
@@ -160,14 +160,14 @@ 
        "UMask": "0x10"

    },

    {

        "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",

        "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_DSB_UOPS",

        "SampleAfterValue": "2000003",

        "UMask": "0x10"

    },

    {

        "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",

        "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_MITE_UOPS",

        "SampleAfterValue": "2000003",
@@ -183,7 +183,7 @@ 
        "UMask": "0x30"

    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_UOPS",

        "SampleAfterValue": "2000003",

tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json

+1 −1
Original line number Diff line number Diff line
@@ -509,7 +509,7 @@ 
        "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.",

        "EventCode": "0x03",

        "EventName": "LD_BLOCKS.STORE_FORWARD",

        "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store.  See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",

        "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load.  The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store.  See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual.  The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.",

        "SampleAfterValue": "100003",

        "UMask": "0x2"

    },

tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json

+331 −270

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tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json

+1 −1

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