Commit a9be4549 authored by Miquel Raynal's avatar Miquel Raynal
Browse files

spi: cadence-quadspi: Provide a capability structure 



This controller has DTR support, so advertize it with a capability now
that the spi-controller structure contains this new field. This will
later be used by the core to discriminate whether an operation is
supported or not, in a more generic way than having different helpers.

Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: default avatarPratyush Yadav <p.yadav@ti.com>
Reviewed-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/linux-mtd/20220127091808.1043392-4-miquel.raynal@bootlin.com
parent cb7e96ee

drivers/spi/spi-cadence-quadspi.c

+5 −0
Original line number Diff line number Diff line
@@ -1595,6 +1595,10 @@ static const struct spi_controller_mem_ops cqspi_mem_ops = { 
	.supports_op = cqspi_supports_mem_op,

};



static const struct spi_controller_mem_caps cqspi_mem_caps = {

	.dtr = true,

};



static int cqspi_setup_flash(struct cqspi_st *cqspi)

{

	struct platform_device *pdev = cqspi->pdev;
@@ -1652,6 +1656,7 @@ static int cqspi_probe(struct platform_device *pdev) 
	}

	master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL;

	master->mem_ops = &cqspi_mem_ops;

	master->mem_caps = &cqspi_mem_caps;

	master->dev.of_node = pdev->dev.of_node;



	cqspi = spi_master_get_devdata(master);