Merge series "ASoC: fsl: fix kernel-doc" from Pierre-Louis Bossart... (a9b6f702) · Commits · EulixOS / Software / Kernel

sound/soc/fsl/fsl-asoc-card.c

+9 −12

Original line number	Diff line number	Diff line
		@@ -33,8 +33,7 @@
		#define DAI_FMT_BASE (SND_SOC_DAIFMT_I2S \| SND_SOC_DAIFMT_NB_NF)

		/**
		* CODEC private data
		*
		* struct codec_priv - CODEC private data
		* @mclk_freq: Clock rate of MCLK
		* @mclk_id: MCLK (or main clock) id for set_sysclk()
		* @fll_id: FLL (or secordary clock) id for set_sysclk()
		@@ -48,11 +47,10 @@ struct codec_priv {
		};

		/**
		* CPU private data
		*
		* @sysclk_freq[2]: SYSCLK rates for set_sysclk()
		* @sysclk_dir[2]: SYSCLK directions for set_sysclk()
		* @sysclk_id[2]: SYSCLK ids for set_sysclk()
		* struct cpu_priv - CPU private data
		* @sysclk_freq: SYSCLK rates for set_sysclk()
		* @sysclk_dir: SYSCLK directions for set_sysclk()
		* @sysclk_id: SYSCLK ids for set_sysclk()
		* @slot_width: Slot width of each frame
		*
		* Note: [1] for tx and [0] for rx
		@@ -65,9 +63,8 @@ struct cpu_priv {
		};

		/**
		* Freescale Generic ASOC card private data
		*
		* @dai_link[3]: DAI link structure including normal one and DPCM link
		* struct fsl_asoc_card_priv - Freescale Generic ASOC card private data
		* @dai_link: DAI link structure including normal one and DPCM link
		* @pdev: platform device pointer
		* @codec_priv: CODEC private data
		* @cpu_priv: CPU private data
		@@ -94,8 +91,8 @@ struct fsl_asoc_card_priv {
		char name[32];
		};

		/**
		* This dapm route map exsits for DPCM link only.
		/*
		* This dapm route map exits for DPCM link only.
		* The other routes shall go through Device Tree.
		*
		* Note: keep all ASRC routes in the second half

sound/soc/fsl/fsl_esai.c

+18 −14

Original line number	Diff line number	Diff line
		@@ -22,8 +22,7 @@
		SNDRV_PCM_FMTBIT_S24_LE)

		/**
		* fsl_esai_soc_data: soc specific data
		*
		* struct fsl_esai_soc_data - soc specific data
		* @imx: for imx platform
		* @reset_at_xrun: flags for enable reset operaton
		*/
		@@ -33,8 +32,7 @@ struct fsl_esai_soc_data {
		};

		/**
		* fsl_esai: ESAI private data
		*
		* struct fsl_esai - ESAI private data
		* @dma_params_rx: DMA parameters for receive channel
		* @dma_params_tx: DMA parameters for transmit channel
		* @pdev: platform device pointer
		@@ -49,6 +47,8 @@ struct fsl_esai_soc_data {
		* @fifo_depth: depth of tx/rx FIFO
		* @slot_width: width of each DAI slot
		* @slots: number of slots
		* @tx_mask: slot mask for TX
		* @rx_mask: slot mask for RX
		* @channels: channel num for tx or rx
		* @hck_rate: clock rate of desired HCKx clock
		* @sck_rate: clock rate of desired SCKx clock
		@@ -157,13 +157,15 @@ static irqreturn_t esai_isr(int irq, void *devid)
		}

		/**
		* This function is used to calculate the divisors of psr, pm, fp and it is
		* supposed to be called in set_dai_sysclk() and set_bclk().
		* fsl_esai_divisor_cal - This function is used to calculate the
		* divisors of psr, pm, fp and it is supposed to be called in
		* set_dai_sysclk() and set_bclk().
		*
		* @dai: pointer to DAI
		* @tx: current setting is for playback or capture
		* @ratio: desired overall ratio for the paticipating dividers
		* @usefp: for HCK setting, there is no need to set fp divider
		* @fp: bypass other dividers by setting fp directly if fp != 0
		* @tx: current setting is for playback or capture
		*/
		static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
		bool usefp, u32 fp)
		@@ -250,13 +252,12 @@ static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,
		}

		/**
		* This function mainly configures the clock frequency of MCLK (HCKT/HCKR)
		*
		* @Parameters:
		* clk_id: The clock source of HCKT/HCKR
		* fsl_esai_set_dai_sysclk - configure the clock frequency of MCLK (HCKT/HCKR)
		* @dai: pointer to DAI
		* @clk_id: The clock source of HCKT/HCKR
		* (Input from outside; output from inside, FSYS or EXTAL)
		* freq: The required clock rate of HCKT/HCKR
		* dir: The clock direction of HCKT/HCKR
		* @freq: The required clock rate of HCKT/HCKR
		* @dir: The clock direction of HCKT/HCKR
		*
		* Note: If the direction is input, we do not care about clk_id.
		*/
		@@ -358,7 +359,10 @@ static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
		}

		/**
		* This function configures the related dividers according to the bclk rate
		* fsl_esai_set_bclk - configure the related dividers according to the bclk rate
		* @dai: pointer to DAI
		* @tx: direction boolean
		* @freq: bclk freq
		*/
		static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
		{

sound/soc/fsl/fsl_spdif.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -81,8 +81,8 @@ struct spdif_mixer_control {
		};

		/**
		* fsl_spdif_priv: Freescale SPDIF private data
		*
		* struct fsl_spdif_priv - Freescale SPDIF private data
		* @soc: SPDIF soc data
		* @fsl_spdif_control: SPDIF control data
		* @cpu_dai_drv: cpu dai driver
		* @pdev: platform device pointer
		@@ -100,6 +100,7 @@ struct spdif_mixer_control {
		* @spbaclk: SPBA clock (optional, depending on SoC design)
		* @dma_params_tx: DMA parameters for transmit channel
		* @dma_params_rx: DMA parameters for receive channel
		* @regcache_srpc: regcache for SRPC
		*/
		struct fsl_spdif_priv {
		const struct fsl_spdif_soc_data *soc;

sound/soc/fsl/fsl_ssi_dbg.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -78,7 +78,7 @@ void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *dbg, u32 sisr)
		dbg->stats.tfe0++;
		}

		/**
		/*
		* Show the statistics of a flag only if its interrupt is enabled
		*
		* Compilers will optimize it to a no-op if the interrupt is disabled
		@@ -90,7 +90,7 @@ void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *dbg, u32 sisr)
		} while (0)


		/**
		/*
		* Display the statistics for the current SSI device
		*
		* To avoid confusion, only show those counts that are enabled