Unverified Commit 3bae1719 authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Mark Brown
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ASoC: fsl: fsl_esai: fix kernel-doc 



Fix W=1 warnings. Fix kernel-doc syntax and add missing parameters.

Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Acked-by: default avatarNicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20200702192141.168018-7-pierre-louis.bossart@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 4674bf06

sound/soc/fsl/fsl_esai.c

+18 −14
Original line number Diff line number Diff line
@@ -22,8 +22,7 @@ 
				SNDRV_PCM_FMTBIT_S24_LE)



/**

 * fsl_esai_soc_data: soc specific data

 *

 * struct fsl_esai_soc_data - soc specific data

 * @imx: for imx platform

 * @reset_at_xrun: flags for enable reset operaton

 */
@@ -33,8 +32,7 @@ struct fsl_esai_soc_data { 
};



/**

 * fsl_esai: ESAI private data

 *

 * struct fsl_esai - ESAI private data

 * @dma_params_rx: DMA parameters for receive channel

 * @dma_params_tx: DMA parameters for transmit channel

 * @pdev: platform device pointer
@@ -49,6 +47,8 @@ struct fsl_esai_soc_data { 
 * @fifo_depth: depth of tx/rx FIFO

 * @slot_width: width of each DAI slot

 * @slots: number of slots

 * @tx_mask: slot mask for TX

 * @rx_mask: slot mask for RX

 * @channels: channel num for tx or rx

 * @hck_rate: clock rate of desired HCKx clock

 * @sck_rate: clock rate of desired SCKx clock
@@ -157,13 +157,15 @@ static irqreturn_t esai_isr(int irq, void *devid) 
}



/**

 * This function is used to calculate the divisors of psr, pm, fp and it is

 * supposed to be called in set_dai_sysclk() and set_bclk().

 * fsl_esai_divisor_cal - This function is used to calculate the

 * divisors of psr, pm, fp and it is supposed to be called in

 * set_dai_sysclk() and set_bclk().

 *

 * @dai: pointer to DAI

 * @tx: current setting is for playback or capture

 * @ratio: desired overall ratio for the paticipating dividers

 * @usefp: for HCK setting, there is no need to set fp divider

 * @fp: bypass other dividers by setting fp directly if fp != 0

 * @tx: current setting is for playback or capture

 */

static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio,

				bool usefp, u32 fp)
@@ -250,13 +252,12 @@ static int fsl_esai_divisor_cal(struct snd_soc_dai *dai, bool tx, u32 ratio, 
}



/**

 * This function mainly configures the clock frequency of MCLK (HCKT/HCKR)

 *

 * @Parameters:

 * clk_id: The clock source of HCKT/HCKR

 * fsl_esai_set_dai_sysclk - configure the clock frequency of MCLK (HCKT/HCKR)

 * @dai: pointer to DAI

 * @clk_id: The clock source of HCKT/HCKR

 *	  (Input from outside; output from inside, FSYS or EXTAL)

 * freq: The required clock rate of HCKT/HCKR

 * dir: The clock direction of HCKT/HCKR

 * @freq: The required clock rate of HCKT/HCKR

 * @dir: The clock direction of HCKT/HCKR

 *

 * Note: If the direction is input, we do not care about clk_id.

 */
@@ -358,7 +359,10 @@ static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 
}



/**

 * This function configures the related dividers according to the bclk rate

 * fsl_esai_set_bclk - configure the related dividers according to the bclk rate

 * @dai: pointer to DAI

 * @tx: direction boolean

 * @freq: bclk freq

 */

static int fsl_esai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)

{