Commit a9979e64 authored Jul 15, 2024 by Steve Wilkins Committed by ZhangPeng Aug 04, 2024

spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer

stable inclusion
from stable-v6.6.44
commit 3feda3677e8bbe833c3a62a4091377a08f015b80
bugzilla: https://gitee.com/openeuler/kernel/issues/IAHMJO

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=3feda3677e8bbe833c3a62a4091377a08f015b80



--------------------------------

[ Upstream commit 9cf71eb0faef4bff01df4264841b8465382d7927 ]

While transmitting with rx_len == 0, the RX FIFO is not going to be
emptied in the interrupt handler. A subsequent transfer could then
read crap from the previous transfer out of the RX FIFO into the
start RX buffer. The core provides a register that will empty the RX and
TX FIFOs, so do that before each transfer.

Fixes: 9ac8d176 ("spi: add support for microchip fpga spi controllers")
Signed-off-by: Steve Wilkins <steve.wilkins@raymarine.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20240715-flammable-provoke-459226d08e70@wendy


Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: ZhangPeng <zhangpeng362@huawei.com>

parent c90b9639

drivers/spi/spi-microchip-core.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -91,6 +91,8 @@
		#define REG_CONTROL2 (0x28)
		#define REG_COMMAND (0x2c)
		#define COMMAND_CLRFRAMECNT BIT(4)
		#define COMMAND_TXFIFORST BIT(3)
		#define COMMAND_RXFIFORST BIT(2)
		#define REG_PKTSIZE (0x30)
		#define REG_CMD_SIZE (0x34)
		#define REG_HWSTATUS (0x38)
		@@ -493,6 +495,8 @@ static int mchp_corespi_transfer_one(struct spi_controller *host,
		mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH)
		? FIFO_DEPTH : spi->tx_len);

		mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST \| COMMAND_TXFIFORST);

		mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select);

		while (spi->tx_len)