Commit c90b9639 authored by Steve Wilkins's avatar Steve Wilkins Committed by ZhangPeng
Browse files

spi: microchip-core: fix init function not setting the master and motorola modes 

stable inclusion
from stable-v6.6.44
commit 783f42b77d33d098463abdc0d6bd6be5ed6bacff
bugzilla: https://gitee.com/openeuler/kernel/issues/IAHMJO

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=783f42b77d33d098463abdc0d6bd6be5ed6bacff



--------------------------------

[ Upstream commit 3a5e76283672efddf47cea39ccfe9f5735cc91d5 ]

mchp_corespi_init() reads the CONTROL register, sets the master and
motorola bits, but doesn't write the value back to the register. The
function also doesn't ensure the controller is disabled at the start,
which may present a problem if the controller was used by an
earlier boot stage as some settings (including the mode) can only be
modified while the controller is disabled.

Fixes: 9ac8d176 ("spi: add support for microchip fpga spi controllers")
Signed-off-by: default avatarSteve Wilkins <steve.wilkins@raymarine.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20240715-designing-thus-05f7c26e1da7@wendy


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarZhangPeng <zhangpeng362@huawei.com>
parent f0df34d7

drivers/spi/spi-microchip-core.c

+9 −8
Original line number Diff line number Diff line
@@ -292,17 +292,13 @@ static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi * 
	unsigned long clk_hz;

	u32 control = mchp_corespi_read(spi, REG_CONTROL);



	control |= CONTROL_MASTER;

	control &= ~CONTROL_ENABLE;

	mchp_corespi_write(spi, REG_CONTROL, control);



	control |= CONTROL_MASTER;

	control &= ~CONTROL_MODE_MASK;

	control |= MOTOROLA_MODE;



	mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);



	/* max. possible spi clock rate is the apb clock rate */

	clk_hz = clk_get_rate(spi->clk);

	host->max_speed_hz = clk_hz;



	/*

	 * The controller must be configured so that it doesn't remove Chip

	 * Select until the entire message has been transferred, even if at
@@ -311,11 +307,16 @@ static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi * 
	 * BIGFIFO mode is also enabled, which sets the fifo depth to 32 frames

	 * for the 8 bit transfers that this driver uses.

	 */

	control = mchp_corespi_read(spi, REG_CONTROL);

	control |= CONTROL_SPS | CONTROL_BIGFIFO;



	mchp_corespi_write(spi, REG_CONTROL, control);



	mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);



	/* max. possible spi clock rate is the apb clock rate */

	clk_hz = clk_get_rate(spi->clk);

	host->max_speed_hz = clk_hz;



	mchp_corespi_enable_ints(spi);



	/*