Commit a8f6bbfc authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'stmmac-imx93' 



Clark Wang says:

====================
stmmac: Add eqos and fec support for imx93

This patchset add imx93 support for dwmac-imx glue driver.
There are some changes of GPR implement.
And add fec and eqos nodes for imx93 dts.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents c4791b31 c897dc7f

Documentation/devicetree/bindings/net/fsl,fec.yaml

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ properties: 
              - fsl,imx8mm-fec

              - fsl,imx8mn-fec

              - fsl,imx8mp-fec

              - fsl,imx93-fec

          - const: fsl,imx8mq-fec

          - const: fsl,imx6sx-fec

      - items:

Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml

+3 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
$id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP i.MX8 DWMAC glue layer

title: NXP i.MX8/9 DWMAC glue layer



maintainers:

  - Clark Wang <xiaoning.wang@nxp.com>
@@ -19,6 +19,7 @@ select: 
        enum:

          - nxp,imx8mp-dwmac-eqos

          - nxp,imx8dxl-dwmac-eqos

          - nxp,imx93-dwmac-eqos

  required:

    - compatible
@@ -32,6 +33,7 @@ properties: 
          - enum:

              - nxp,imx8mp-dwmac-eqos

              - nxp,imx8dxl-dwmac-eqos

              - nxp,imx93-dwmac-eqos

          - const: snps,dwmac-5.10a



  clocks:

arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts

+78 −0
Original line number Diff line number Diff line
@@ -35,6 +35,46 @@ 
	status = "okay";

};



&eqos {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_eqos>;

	phy-mode = "rgmii-id";

	phy-handle = <&ethphy1>;

	status = "okay";



	mdio {

		compatible = "snps,dwmac-mdio";

		#address-cells = <1>;

		#size-cells = <0>;

		clock-frequency = <5000000>;



		ethphy1: ethernet-phy@1 {

			reg = <1>;

			eee-broken-1000t;

		};

	};

};



&fec {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_fec>;

	phy-mode = "rgmii-id";

	phy-handle = <&ethphy2>;

	fsl,magic-packet;

	status = "okay";



	mdio {

		#address-cells = <1>;

		#size-cells = <0>;

		clock-frequency = <5000000>;



		ethphy2: ethernet-phy@2 {

			reg = <2>;

			eee-broken-1000t;

		};

	};

};



&lpuart1 { /* console */

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart1>;
@@ -65,6 +105,44 @@ 
};



&iomuxc {

	pinctrl_eqos: eqosgrp {

		fsl,pins = <

			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x57e

			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e

			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e

			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e

			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e

			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e

			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x5fe

			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e

			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e

			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x57e

			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e

			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e

			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x5fe

			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e

		>;

	};



	pinctrl_fec: fecgrp {

		fsl,pins = <

			MX93_PAD_ENET2_MDC__ENET1_MDC			0x57e

			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x57e

			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e

			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e

			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e

			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e

			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x5fe

			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e

			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x57e

			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x57e

			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x57e

			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x57e

			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x5fe

			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x57e

		>;

	};



	pinctrl_uart1: uart1grp {

		fsl,pins = <

			MX93_PAD_UART1_RXD__LPUART1_RX			0x31e

arch/arm64/boot/dts/freescale/imx93.dtsi

+48 −0
Original line number Diff line number Diff line
@@ -536,6 +536,54 @@ 
				status = "disabled";

			};



			eqos: ethernet@428a0000 {

				compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";

				reg = <0x428a0000 0x10000>;

				interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names = "eth_wake_irq", "macirq";

				clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,

					 <&clk IMX93_CLK_ENET_QOS_GATE>,

					 <&clk IMX93_CLK_ENET_TIMER2>,

					 <&clk IMX93_CLK_ENET>,

					 <&clk IMX93_CLK_ENET_QOS_GATE>;

				clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";

				assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,

						  <&clk IMX93_CLK_ENET>;

				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,

							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;

				assigned-clock-rates = <100000000>, <250000000>;

				intf_mode = <&wakeupmix_gpr 0x28>;

				clk_csr = <0>;

				status = "disabled";

			};



			fec: ethernet@42890000 {

				compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";

				reg = <0x42890000 0x10000>;

				interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX93_CLK_ENET1_GATE>,

					 <&clk IMX93_CLK_ENET1_GATE>,

					 <&clk IMX93_CLK_ENET_TIMER1>,

					 <&clk IMX93_CLK_ENET_REF>,

					 <&clk IMX93_CLK_ENET_REF_PHY>;

				clock-names = "ipg", "ahb", "ptp",

					      "enet_clk_ref", "enet_out";

				assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,

						  <&clk IMX93_CLK_ENET_REF>,

						  <&clk IMX93_CLK_ENET_REF_PHY>;

				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,

							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,

							 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;

				assigned-clock-rates = <100000000>, <250000000>, <50000000>;

				fsl,num-tx-queues = <3>;

				fsl,num-rx-queues = <3>;

				status = "disabled";

			};



			usdhc3: mmc@428b0000 {

				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";

				reg = <0x428b0000 0x10000>;

drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c

+50 −5
Original line number Diff line number Diff line
@@ -31,6 +31,12 @@ 
#define GPR_ENET_QOS_CLK_TX_CLK_SEL	(0x1 << 20)

#define GPR_ENET_QOS_RGMII_EN		(0x1 << 21)



#define MX93_GPR_ENET_QOS_INTF_MODE_MASK	GENMASK(3, 0)

#define MX93_GPR_ENET_QOS_INTF_SEL_MII		(0x0 << 1)

#define MX93_GPR_ENET_QOS_INTF_SEL_RMII		(0x4 << 1)

#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII	(0x1 << 1)

#define MX93_GPR_ENET_QOS_CLK_GEN_EN		(0x1 << 0)



struct imx_dwmac_ops {

	u32 addr_width;

	bool mac_rgmii_txclk_auto_adj;
@@ -90,6 +96,35 @@ imx8dxl_set_intf_mode(struct plat_stmmacenet_data *plat_dat) 
	return ret;

}



static int imx93_set_intf_mode(struct plat_stmmacenet_data *plat_dat)

{

	struct imx_priv_data *dwmac = plat_dat->bsp_priv;

	int val;



	switch (plat_dat->interface) {

	case PHY_INTERFACE_MODE_MII:

		val = MX93_GPR_ENET_QOS_INTF_SEL_MII;

		break;

	case PHY_INTERFACE_MODE_RMII:

		val = MX93_GPR_ENET_QOS_INTF_SEL_RMII;

		break;

	case PHY_INTERFACE_MODE_RGMII:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

	case PHY_INTERFACE_MODE_RGMII_TXID:

		val = MX93_GPR_ENET_QOS_INTF_SEL_RGMII;

		break;

	default:

		dev_dbg(dwmac->dev, "imx dwmac doesn't support %d interface\n",

			 plat_dat->interface);

		return -EINVAL;

	}



	val |= MX93_GPR_ENET_QOS_CLK_GEN_EN;

	return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,

				  MX93_GPR_ENET_QOS_INTF_MODE_MASK, val);

};



static int imx_dwmac_clks_config(void *priv, bool enabled)

{

	struct imx_priv_data *dwmac = priv;
@@ -188,7 +223,9 @@ imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev) 
	}



	dwmac->clk_mem = NULL;

	if (of_machine_is_compatible("fsl,imx8dxl")) {



	if (of_machine_is_compatible("fsl,imx8dxl") ||

	    of_machine_is_compatible("fsl,imx93")) {

		dwmac->clk_mem = devm_clk_get(dev, "mem");

		if (IS_ERR(dwmac->clk_mem)) {

			dev_err(dev, "failed to get mem clock\n");
@@ -196,10 +233,11 @@ imx_dwmac_parse_dt(struct imx_priv_data *dwmac, struct device *dev) 
		}

	}



	if (of_machine_is_compatible("fsl,imx8mp")) {

		/* Binding doc describes the property:

		   is required by i.MX8MP.

		   is optional for i.MX8DXL.

	if (of_machine_is_compatible("fsl,imx8mp") ||

	    of_machine_is_compatible("fsl,imx93")) {

		/* Binding doc describes the propety:

		 * is required by i.MX8MP, i.MX93.

		 * is optinoal for i.MX8DXL.

		 */

		dwmac->intf_regmap = syscon_regmap_lookup_by_phandle(np, "intf_mode");

		if (IS_ERR(dwmac->intf_regmap))
@@ -296,9 +334,16 @@ static struct imx_dwmac_ops imx8dxl_dwmac_data = { 
	.set_intf_mode = imx8dxl_set_intf_mode,

};



static struct imx_dwmac_ops imx93_dwmac_data = {

	.addr_width = 32,

	.mac_rgmii_txclk_auto_adj = true,

	.set_intf_mode = imx93_set_intf_mode,

};



static const struct of_device_id imx_dwmac_match[] = {

	{ .compatible = "nxp,imx8mp-dwmac-eqos", .data = &imx8mp_dwmac_data },

	{ .compatible = "nxp,imx8dxl-dwmac-eqos", .data = &imx8dxl_dwmac_data },

	{ .compatible = "nxp,imx93-dwmac-eqos", .data = &imx93_dwmac_data },

	{ }

};

MODULE_DEVICE_TABLE(of, imx_dwmac_match);