Commit c4791b31 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'net-mdio-continue-separating-c22-and-c45' 

Michael Walle says:

====================
net: mdio: Continue separating C22 and C45

I've picked this older series from Andrew up and rebased it onto
the latest net-next.

This is the third (and hopefully last) patch set in the series which
separates the C22 and C45 MDIO bus transactions at the API level to the
MDIO bus drivers.

The first patch is a newer version of the former "net: dsa: Separate C22
and C45 MDIO bus transaction methods", which only contains the mt7530
changes. Although posted as v1, because this is a new series, there
is a changelog included in the patch comment section.

The last patch is a new one, which isn't from Andrew's tree.
====================

Link: https://lore.kernel.org/r/20230116-net-next-c45-seperation-part-3-v1-0-0c53afa56aad@walle.cc


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 860edff5 95331514

drivers/net/dsa/mt7530.c

+44 −43
Original line number Diff line number Diff line
@@ -608,17 +608,29 @@ mt7530_mib_reset(struct dsa_switch *ds) 
	mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);

}



static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum)

static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum)

{

	return mdiobus_read_nested(priv->bus, port, regnum);

}



static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum,

static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum,

				u16 val)

{

	return mdiobus_write_nested(priv->bus, port, regnum, val);

}



static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port,

			       int devad, int regnum)

{

	return mdiobus_c45_read_nested(priv->bus, port, devad, regnum);

}



static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad,

				int regnum, u16 val)

{

	return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val);

}



static int

mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,

			int regnum)
@@ -670,7 +682,7 @@ mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 


static int

mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,

			 int regnum, u32 data)

			 int regnum, u16 data)

{

	struct mii_bus *bus = priv->bus;

	struct mt7530_dummy_poll p;
@@ -793,55 +805,36 @@ mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 
}



static int

mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum)

mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum)

{

	int devad;

	int ret;

	struct mt7530_priv *priv = bus->priv;



	if (regnum & MII_ADDR_C45) {

		devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;

		ret = mt7531_ind_c45_phy_read(priv, port, devad,

					      regnum & MII_REGADDR_C45_MASK);

	} else {

		ret = mt7531_ind_c22_phy_read(priv, port, regnum);

	}



	return ret;

	return priv->info->phy_read_c22(priv, port, regnum);

}



static int

mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum,

		     u16 data)

mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum)

{

	int devad;

	int ret;



	if (regnum & MII_ADDR_C45) {

		devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;

		ret = mt7531_ind_c45_phy_write(priv, port, devad,

					       regnum & MII_REGADDR_C45_MASK,

					       data);

	} else {

		ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);

	}

	struct mt7530_priv *priv = bus->priv;



	return ret;

	return priv->info->phy_read_c45(priv, port, devad, regnum);

}



static int

mt753x_phy_read(struct mii_bus *bus, int port, int regnum)

mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val)

{

	struct mt7530_priv *priv = bus->priv;



	return priv->info->phy_read(priv, port, regnum);

	return priv->info->phy_write_c22(priv, port, regnum, val);

}



static int

mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val)

mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum,

		     u16 val)

{

	struct mt7530_priv *priv = bus->priv;



	return priv->info->phy_write(priv, port, regnum, val);

	return priv->info->phy_write_c45(priv, port, devad, regnum, val);

}



static void
@@ -2086,8 +2079,10 @@ mt7530_setup_mdio(struct mt7530_priv *priv) 
	bus->priv = priv;

	bus->name = KBUILD_MODNAME "-mii";

	snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);

	bus->read = mt753x_phy_read;

	bus->write = mt753x_phy_write;

	bus->read = mt753x_phy_read_c22;

	bus->write = mt753x_phy_write_c22;

	bus->read_c45 = mt753x_phy_read_c45;

	bus->write_c45 = mt753x_phy_write_c45;

	bus->parent = dev;

	bus->phy_mask = ~ds->phys_mii_mask;
@@ -3182,8 +3177,10 @@ static const struct mt753x_info mt753x_table[] = { 
		.id = ID_MT7621,

		.pcs_ops = &mt7530_pcs_ops,

		.sw_setup = mt7530_setup,

		.phy_read = mt7530_phy_read,

		.phy_write = mt7530_phy_write,

		.phy_read_c22 = mt7530_phy_read_c22,

		.phy_write_c22 = mt7530_phy_write_c22,

		.phy_read_c45 = mt7530_phy_read_c45,

		.phy_write_c45 = mt7530_phy_write_c45,

		.pad_setup = mt7530_pad_clk_setup,

		.mac_port_get_caps = mt7530_mac_port_get_caps,

		.mac_port_config = mt7530_mac_config,
@@ -3192,8 +3189,10 @@ static const struct mt753x_info mt753x_table[] = { 
		.id = ID_MT7530,

		.pcs_ops = &mt7530_pcs_ops,

		.sw_setup = mt7530_setup,

		.phy_read = mt7530_phy_read,

		.phy_write = mt7530_phy_write,

		.phy_read_c22 = mt7530_phy_read_c22,

		.phy_write_c22 = mt7530_phy_write_c22,

		.phy_read_c45 = mt7530_phy_read_c45,

		.phy_write_c45 = mt7530_phy_write_c45,

		.pad_setup = mt7530_pad_clk_setup,

		.mac_port_get_caps = mt7530_mac_port_get_caps,

		.mac_port_config = mt7530_mac_config,
@@ -3202,8 +3201,10 @@ static const struct mt753x_info mt753x_table[] = { 
		.id = ID_MT7531,

		.pcs_ops = &mt7531_pcs_ops,

		.sw_setup = mt7531_setup,

		.phy_read = mt7531_ind_phy_read,

		.phy_write = mt7531_ind_phy_write,

		.phy_read_c22 = mt7531_ind_c22_phy_read,

		.phy_write_c22 = mt7531_ind_c22_phy_write,

		.phy_read_c45 = mt7531_ind_c45_phy_read,

		.phy_write_c45 = mt7531_ind_c45_phy_write,

		.pad_setup = mt7531_pad_setup,

		.cpu_port_config = mt7531_cpu_port_config,

		.mac_port_get_caps = mt7531_mac_port_get_caps,
@@ -3263,7 +3264,7 @@ mt7530_probe(struct mdio_device *mdiodev) 
	 * properly.

	 */

	if (!priv->info->sw_setup || !priv->info->pad_setup ||

	    !priv->info->phy_read || !priv->info->phy_write ||

	    !priv->info->phy_read_c22 || !priv->info->phy_write_c22 ||

	    !priv->info->mac_port_get_caps ||

	    !priv->info->mac_port_config)

		return -EINVAL;

drivers/net/dsa/mt7530.h

+11 −4
Original line number Diff line number Diff line
@@ -750,8 +750,10 @@ struct mt753x_pcs { 
/* struct mt753x_info -	This is the main data structure for holding the specific

 *			part for each supported device

 * @sw_setup:		Holding the handler to a device initialization

 * @phy_read:		Holding the way reading PHY port

 * @phy_write:		Holding the way writing PHY port

 * @phy_read_c22:	Holding the way reading PHY port using C22

 * @phy_write_c22:	Holding the way writing PHY port using C22

 * @phy_read_c45:	Holding the way reading PHY port using C45

 * @phy_write_c45:	Holding the way writing PHY port using C45

 * @pad_setup:		Holding the way setting up the bus pad for a certain

 *			MAC port

 * @phy_mode_supported:	Check if the PHY type is being supported on a certain
@@ -767,8 +769,13 @@ struct mt753x_info { 
	const struct phylink_pcs_ops *pcs_ops;



	int (*sw_setup)(struct dsa_switch *ds);

	int (*phy_read)(struct mt7530_priv *priv, int port, int regnum);

	int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);

	int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum);

	int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum,

			     u16 val);

	int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad,

			    int regnum);

	int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,

			     int regnum, u16 val);

	int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);

	int (*cpu_port_config)(struct dsa_switch *ds, int port);

	void (*mac_port_get_caps)(struct dsa_switch *ds, int port,

drivers/net/dsa/sja1105/sja1105.h

+10 −6
Original line number Diff line number Diff line
@@ -149,8 +149,10 @@ struct sja1105_info { 
	bool (*rxtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);

	void (*txtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb);

	int (*clocking_setup)(struct sja1105_private *priv);

	int (*pcs_mdio_read)(struct mii_bus *bus, int phy, int reg);

	int (*pcs_mdio_write)(struct mii_bus *bus, int phy, int reg, u16 val);

	int (*pcs_mdio_read_c45)(struct mii_bus *bus, int phy, int mmd,

				 int reg);

	int (*pcs_mdio_write_c45)(struct mii_bus *bus, int phy, int mmd,

				  int reg, u16 val);

	int (*disable_microcontroller)(struct sja1105_private *priv);

	const char *name;

	bool supports_mii[SJA1105_MAX_NUM_PORTS];
@@ -303,10 +305,12 @@ void sja1105_frame_memory_partitioning(struct sja1105_private *priv); 
/* From sja1105_mdio.c */

int sja1105_mdiobus_register(struct dsa_switch *ds);

void sja1105_mdiobus_unregister(struct dsa_switch *ds);

int sja1105_pcs_mdio_read(struct mii_bus *bus, int phy, int reg);

int sja1105_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val);

int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg);

int sja1110_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val);

int sja1105_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg);

int sja1105_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, int reg,

			       u16 val);

int sja1110_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg);

int sja1110_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd, int reg,

			       u16 val);



/* From sja1105_devlink.c */

int sja1105_devlink_setup(struct dsa_switch *ds);

drivers/net/dsa/sja1105/sja1105_mdio.c

+56 −75
Original line number Diff line number Diff line
@@ -7,20 +7,15 @@ 


#define SJA1110_PCS_BANK_REG		SJA1110_SPI_ADDR(0x3fc)



int sja1105_pcs_mdio_read(struct mii_bus *bus, int phy, int reg)

int sja1105_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg)

{

	struct sja1105_mdio_private *mdio_priv = bus->priv;

	struct sja1105_private *priv = mdio_priv->priv;

	u64 addr;

	u32 tmp;

	u16 mmd;

	int rc;



	if (!(reg & MII_ADDR_C45))

		return -EINVAL;



	mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;

	addr = (mmd << 16) | (reg & GENMASK(15, 0));

	addr = (mmd << 16) | reg;



	if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2)

		return 0xffff;
@@ -37,19 +32,15 @@ int sja1105_pcs_mdio_read(struct mii_bus *bus, int phy, int reg) 
	return tmp & 0xffff;

}



int sja1105_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)

int sja1105_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int mmd,

			       int reg, u16 val)

{

	struct sja1105_mdio_private *mdio_priv = bus->priv;

	struct sja1105_private *priv = mdio_priv->priv;

	u64 addr;

	u32 tmp;

	u16 mmd;



	if (!(reg & MII_ADDR_C45))

		return -EINVAL;



	mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;

	addr = (mmd << 16) | (reg & GENMASK(15, 0));

	addr = (mmd << 16) | reg;

	tmp = val;



	if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2)
@@ -58,7 +49,7 @@ int sja1105_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 
	return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);

}



int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg)

int sja1110_pcs_mdio_read_c45(struct mii_bus *bus, int phy, int mmd, int reg)

{

	struct sja1105_mdio_private *mdio_priv = bus->priv;

	struct sja1105_private *priv = mdio_priv->priv;
@@ -66,17 +57,12 @@ int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg) 
	int offset, bank;

	u64 addr;

	u32 tmp;

	u16 mmd;

	int rc;



	if (!(reg & MII_ADDR_C45))

		return -EINVAL;



	if (regs->pcs_base[phy] == SJA1105_RSV_ADDR)

		return -ENODEV;



	mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;

	addr = (mmd << 16) | (reg & GENMASK(15, 0));

	addr = (mmd << 16) | reg;



	if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1)

		return NXP_SJA1110_XPCS_ID >> 16;
@@ -108,7 +94,8 @@ int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg) 
	return tmp & 0xffff;

}



int sja1110_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)

int sja1110_pcs_mdio_write_c45(struct mii_bus *bus, int phy, int reg, int mmd,

			       u16 val)

{

	struct sja1105_mdio_private *mdio_priv = bus->priv;

	struct sja1105_private *priv = mdio_priv->priv;
@@ -116,17 +103,12 @@ int sja1110_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 
	int offset, bank;

	u64 addr;

	u32 tmp;

	u16 mmd;

	int rc;



	if (!(reg & MII_ADDR_C45))

		return -EINVAL;



	if (regs->pcs_base[phy] == SJA1105_RSV_ADDR)

		return -ENODEV;



	mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;

	addr = (mmd << 16) | (reg & GENMASK(15, 0));

	addr = (mmd << 16) | reg;



	bank = addr >> 8;

	offset = addr & GENMASK(7, 0);
@@ -167,7 +149,7 @@ static u64 sja1105_base_t1_encode_addr(struct sja1105_private *priv, 
	return regs->mdio_100base_t1 | (phy << 7) | (op << 5) | (xad << 0);

}



static int sja1105_base_t1_mdio_read(struct mii_bus *bus, int phy, int reg)

static int sja1105_base_t1_mdio_read_c22(struct mii_bus *bus, int phy, int reg)

{

	struct sja1105_mdio_private *mdio_priv = bus->priv;

	struct sja1105_private *priv = mdio_priv->priv;
@@ -175,20 +157,7 @@ static int sja1105_base_t1_mdio_read(struct mii_bus *bus, int phy, int reg) 
	u32 tmp;

	int rc;



	if (reg & MII_ADDR_C45) {

		u16 mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;



		addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR,

						   mmd);



		tmp = reg & MII_REGADDR_C45_MASK;



		rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);

		if (rc < 0)

			return rc;



		addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA,

						   mmd);

	addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);



	rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);

	if (rc < 0)
@@ -197,8 +166,22 @@ static int sja1105_base_t1_mdio_read(struct mii_bus *bus, int phy, int reg) 
	return tmp & 0xffff;

}



	/* Clause 22 read */

	addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);

static int sja1105_base_t1_mdio_read_c45(struct mii_bus *bus, int phy,

					 int mmd, int reg)

{

	struct sja1105_mdio_private *mdio_priv = bus->priv;

	struct sja1105_private *priv = mdio_priv->priv;

	u64 addr;

	u32 tmp;

	int rc;



	addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR, mmd);



	rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &reg, NULL);

	if (rc < 0)

		return rc;



	addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA, mmd);



	rc = sja1105_xfer_u32(priv, SPI_READ, addr, &tmp, NULL);

	if (rc < 0)
@@ -207,41 +190,37 @@ static int sja1105_base_t1_mdio_read(struct mii_bus *bus, int phy, int reg) 
	return tmp & 0xffff;

}



static int sja1105_base_t1_mdio_write(struct mii_bus *bus, int phy, int reg,

static int sja1105_base_t1_mdio_write_c22(struct mii_bus *bus, int phy, int reg,

					  u16 val)

{

	struct sja1105_mdio_private *mdio_priv = bus->priv;

	struct sja1105_private *priv = mdio_priv->priv;

	u64 addr;

	u32 tmp;

	int rc;



	if (reg & MII_ADDR_C45) {

		u16 mmd = (reg >> MII_DEVADDR_C45_SHIFT) & 0x1f;



		addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR,

						   mmd);

	addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);



		tmp = reg & MII_REGADDR_C45_MASK;

	tmp = val & 0xffff;



		rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);

		if (rc < 0)

			return rc;

	return sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);

}



		addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA,

						   mmd);

static int sja1105_base_t1_mdio_write_c45(struct mii_bus *bus, int phy,

					  int mmd, int reg, u16 val)

{

	struct sja1105_mdio_private *mdio_priv = bus->priv;

	struct sja1105_private *priv = mdio_priv->priv;

	u64 addr;

	u32 tmp;

	int rc;



		tmp = val & 0xffff;

	addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_ADDR, mmd);



		rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &tmp, NULL);

	rc = sja1105_xfer_u32(priv, SPI_WRITE, addr, &reg, NULL);

	if (rc < 0)

		return rc;



		return 0;

	}



	/* Clause 22 write */

	addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C22, reg & 0x1f);

	addr = sja1105_base_t1_encode_addr(priv, phy, SJA1105_C45_DATA, mmd);



	tmp = val & 0xffff;
@@ -360,8 +339,10 @@ static int sja1105_mdiobus_base_t1_register(struct sja1105_private *priv, 
	bus->name = "SJA1110 100base-T1 MDIO bus";

	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-base-t1",

		 dev_name(priv->ds->dev));

	bus->read = sja1105_base_t1_mdio_read;

	bus->write = sja1105_base_t1_mdio_write;

	bus->read = sja1105_base_t1_mdio_read_c22;

	bus->write = sja1105_base_t1_mdio_write_c22;

	bus->read_c45 = sja1105_base_t1_mdio_read_c45;

	bus->write_c45 = sja1105_base_t1_mdio_write_c45;

	bus->parent = priv->ds->dev;

	mdio_priv = bus->priv;

	mdio_priv->priv = priv;
@@ -398,7 +379,7 @@ static int sja1105_mdiobus_pcs_register(struct sja1105_private *priv) 
	int rc = 0;

	int port;



	if (!priv->info->pcs_mdio_read || !priv->info->pcs_mdio_write)

	if (!priv->info->pcs_mdio_read_c45 || !priv->info->pcs_mdio_write_c45)

		return 0;



	bus = mdiobus_alloc_size(sizeof(*mdio_priv));
@@ -408,8 +389,8 @@ static int sja1105_mdiobus_pcs_register(struct sja1105_private *priv) 
	bus->name = "SJA1105 PCS MDIO bus";

	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-pcs",

		 dev_name(ds->dev));

	bus->read = priv->info->pcs_mdio_read;

	bus->write = priv->info->pcs_mdio_write;

	bus->read_c45 = priv->info->pcs_mdio_read_c45;

	bus->write_c45 = priv->info->pcs_mdio_write_c45;

	bus->parent = ds->dev;

	/* There is no PHY on this MDIO bus => mask out all PHY addresses

	 * from auto probing.

drivers/net/dsa/sja1105/sja1105_spi.c

+12 −12
Original line number Diff line number Diff line
@@ -719,8 +719,8 @@ const struct sja1105_info sja1105r_info = { 
	.ptp_cmd_packing	= sja1105pqrs_ptp_cmd_packing,

	.rxtstamp		= sja1105_rxtstamp,

	.clocking_setup		= sja1105_clocking_setup,

	.pcs_mdio_read		= sja1105_pcs_mdio_read,

	.pcs_mdio_write		= sja1105_pcs_mdio_write,

	.pcs_mdio_read_c45	= sja1105_pcs_mdio_read_c45,

	.pcs_mdio_write_c45	= sja1105_pcs_mdio_write_c45,

	.regs			= &sja1105pqrs_regs,

	.port_speed		= {

		[SJA1105_SPEED_AUTO] = 0,
@@ -756,8 +756,8 @@ const struct sja1105_info sja1105s_info = { 
	.ptp_cmd_packing	= sja1105pqrs_ptp_cmd_packing,

	.rxtstamp		= sja1105_rxtstamp,

	.clocking_setup		= sja1105_clocking_setup,

	.pcs_mdio_read		= sja1105_pcs_mdio_read,

	.pcs_mdio_write		= sja1105_pcs_mdio_write,

	.pcs_mdio_read_c45	= sja1105_pcs_mdio_read_c45,

	.pcs_mdio_write_c45	= sja1105_pcs_mdio_write_c45,

	.port_speed		= {

		[SJA1105_SPEED_AUTO] = 0,

		[SJA1105_SPEED_10MBPS] = 3,
@@ -794,8 +794,8 @@ const struct sja1105_info sja1110a_info = { 
	.rxtstamp		= sja1110_rxtstamp,

	.txtstamp		= sja1110_txtstamp,

	.disable_microcontroller = sja1110_disable_microcontroller,

	.pcs_mdio_read		= sja1110_pcs_mdio_read,

	.pcs_mdio_write		= sja1110_pcs_mdio_write,

	.pcs_mdio_read_c45	= sja1110_pcs_mdio_read_c45,

	.pcs_mdio_write_c45	= sja1110_pcs_mdio_write_c45,

	.port_speed		= {

		[SJA1105_SPEED_AUTO] = 0,

		[SJA1105_SPEED_10MBPS] = 4,
@@ -844,8 +844,8 @@ const struct sja1105_info sja1110b_info = { 
	.rxtstamp		= sja1110_rxtstamp,

	.txtstamp		= sja1110_txtstamp,

	.disable_microcontroller = sja1110_disable_microcontroller,

	.pcs_mdio_read		= sja1110_pcs_mdio_read,

	.pcs_mdio_write		= sja1110_pcs_mdio_write,

	.pcs_mdio_read_c45	= sja1110_pcs_mdio_read_c45,

	.pcs_mdio_write_c45	= sja1110_pcs_mdio_write_c45,

	.port_speed		= {

		[SJA1105_SPEED_AUTO] = 0,

		[SJA1105_SPEED_10MBPS] = 4,
@@ -894,8 +894,8 @@ const struct sja1105_info sja1110c_info = { 
	.rxtstamp		= sja1110_rxtstamp,

	.txtstamp		= sja1110_txtstamp,

	.disable_microcontroller = sja1110_disable_microcontroller,

	.pcs_mdio_read		= sja1110_pcs_mdio_read,

	.pcs_mdio_write		= sja1110_pcs_mdio_write,

	.pcs_mdio_read_c45	= sja1110_pcs_mdio_read_c45,

	.pcs_mdio_write_c45	= sja1110_pcs_mdio_write_c45,

	.port_speed		= {

		[SJA1105_SPEED_AUTO] = 0,

		[SJA1105_SPEED_10MBPS] = 4,
@@ -944,8 +944,8 @@ const struct sja1105_info sja1110d_info = { 
	.rxtstamp		= sja1110_rxtstamp,

	.txtstamp		= sja1110_txtstamp,

	.disable_microcontroller = sja1110_disable_microcontroller,

	.pcs_mdio_read		= sja1110_pcs_mdio_read,

	.pcs_mdio_write		= sja1110_pcs_mdio_write,

	.pcs_mdio_read_c45	= sja1110_pcs_mdio_read_c45,

	.pcs_mdio_write_c45	= sja1110_pcs_mdio_write_c45,

	.port_speed		= {

		[SJA1105_SPEED_AUTO] = 0,

		[SJA1105_SPEED_10MBPS] = 4,