Commit a8b5aef2 authored by Bitterblue Smith's avatar Bitterblue Smith Committed by Kalle Valo
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wifi: rtl8xxxu: gen2: Enable 40 MHz channel width



The module parameter ht40_2g was supposed to enable 40 MHz operation,
but it didn't.

Tell the firmware about the channel width when updating the rate mask.
This makes it work with my gen 2 chip RTL8188FU.

I'm not sure if anything needs to be done for the gen 1 chips, if 40
MHz channel width already works or not. They update the rate mask with
a different structure which doesn't have a field for the channel width.

Also set the channel width correctly for sta_statistics.

Fixes: f653e690 ("rtl8xxxu: Implement basic 8723b specific update_rate_mask() function")
Fixes: bd917b3d ("rtl8xxxu: fill up txrate info for gen1 chips")
Signed-off-by: default avatarBitterblue Smith <rtl8821cerfe2@gmail.com>
Acked-by: default avatarJes Sorensen <jes@trained-monkey.org>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/3a950997-7580-8a6b-97a0-e0a81a135456@gmail.com
parent a1cb0971
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+3 −3
Original line number Diff line number Diff line
@@ -1425,7 +1425,7 @@ struct rtl8xxxu_fileops {
	void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel,
			      bool ht40);
	void (*update_rate_mask) (struct rtl8xxxu_priv *priv,
				  u32 ramask, u8 rateid, int sgi);
				  u32 ramask, u8 rateid, int sgi, int txbw_40mhz);
	void (*report_connect) (struct rtl8xxxu_priv *priv,
				u8 macid, bool connect);
	void (*fill_txdesc) (struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
@@ -1511,9 +1511,9 @@ void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw);
void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv);
void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv);
void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
			       u32 ramask, u8 rateid, int sgi);
			       u32 ramask, u8 rateid, int sgi, int txbw_40mhz);
void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
				    u32 ramask, u8 rateid, int sgi);
				    u32 ramask, u8 rateid, int sgi, int txbw_40mhz);
void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
				  u8 macid, bool connect);
void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
+15 −6
Original line number Diff line number Diff line
@@ -4320,7 +4320,7 @@ static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
}

void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
			       u32 ramask, u8 rateid, int sgi)
			       u32 ramask, u8 rateid, int sgi, int txbw_40mhz)
{
	struct h2c_cmd h2c;

@@ -4340,10 +4340,15 @@ void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
}

void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
				    u32 ramask, u8 rateid, int sgi)
				    u32 ramask, u8 rateid, int sgi, int txbw_40mhz)
{
	struct h2c_cmd h2c;
	u8 bw = RTL8XXXU_CHANNEL_WIDTH_20;
	u8 bw;

	if (txbw_40mhz)
		bw = RTL8XXXU_CHANNEL_WIDTH_40;
	else
		bw = RTL8XXXU_CHANNEL_WIDTH_20;

	memset(&h2c, 0, sizeof(struct h2c_cmd));

@@ -4621,7 +4626,11 @@ rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
						RATE_INFO_FLAGS_SHORT_GI;
				}

				rarpt->txrate.bw |= RATE_INFO_BW_20;
				if (rtl8xxxu_ht40_2g &&
				    (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40))
					rarpt->txrate.bw = RATE_INFO_BW_40;
				else
					rarpt->txrate.bw = RATE_INFO_BW_20;
			}
			bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate);
			rarpt->bit_rate = bit_rate;
@@ -4630,7 +4639,7 @@ rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
			priv->vif = vif;
			priv->rssi_level = RTL8XXXU_RATR_STA_INIT;

			priv->fops->update_rate_mask(priv, ramask, 0, sgi);
			priv->fops->update_rate_mask(priv, ramask, 0, sgi, rarpt->txrate.bw == RATE_INFO_BW_40);

			rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);

@@ -6344,7 +6353,7 @@ static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv,
		}

		priv->rssi_level = rssi_level;
		priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi);
		priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz);
	}
}