Commit a1cb0971 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
Browse files

wifi: rtw89: 8852b: configure DLE mem 



Configure DLE (data link engine) memory size for operating modes.

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220927062611.30484-10-pkshih@realtek.com
parent 5f8c35b9

drivers/net/wireless/realtek/rtw89/mac.c

+14 −0
Original line number Diff line number Diff line
@@ -1256,6 +1256,10 @@ const struct rtw89_mac_size_set rtw89_mac_size = { 
	.wde_size0 = {RTW89_WDE_PG_64, 4095, 1,},

	/* DLFW */

	.wde_size4 = {RTW89_WDE_PG_64, 0, 4096,},

	/* PCIE 64 */

	.wde_size6 = {RTW89_WDE_PG_64, 512, 0,},

	/* DLFW */

	.wde_size9 = {RTW89_WDE_PG_64, 0, 1024,},

	/* 8852C DLFW */

	.wde_size18 = {RTW89_WDE_PG_64, 0, 2048,},

	/* 8852C PCIE SCC */
@@ -1264,6 +1268,10 @@ const struct rtw89_mac_size_set rtw89_mac_size = { 
	.ple_size0 = {RTW89_PLE_PG_128, 1520, 16,},

	/* DLFW */

	.ple_size4 = {RTW89_PLE_PG_128, 64, 1472,},

	/* PCIE 64 */

	.ple_size6 = {RTW89_PLE_PG_128, 496, 16,},

	/* DLFW */

	.ple_size8 = {RTW89_PLE_PG_128, 64, 960,},

	/* 8852C DLFW */

	.ple_size18 = {RTW89_PLE_PG_128, 2544, 16,},

	/* 8852C PCIE SCC */
@@ -1272,6 +1280,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = { 
	.wde_qt0 = {3792, 196, 0, 107,},

	/* DLFW */

	.wde_qt4 = {0, 0, 0, 0,},

	/* PCIE 64 */

	.wde_qt6 = {448, 48, 0, 16,},

	/* 8852C DLFW */

	.wde_qt17 = {0, 0, 0,  0,},

	/* 8852C PCIE SCC */
@@ -1282,6 +1292,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = { 
	.ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,},

	/* DLFW */

	.ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,},

	/* PCIE 64 */

	.ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,},

	/* DLFW 52C */

	.ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,},

	/* DLFW 52C */
@@ -1290,6 +1302,8 @@ const struct rtw89_mac_size_set rtw89_mac_size = { 
	.ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,},

	/* 8852C PCIE SCC */

	.ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,},

	/* PCIE 64 */

	.ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,},

};

EXPORT_SYMBOL(rtw89_mac_size);

drivers/net/wireless/realtek/rtw89/mac.h

+7 −0
Original line number Diff line number Diff line
@@ -691,23 +691,30 @@ struct rtw89_mac_size_set { 
	const struct rtw89_hfc_prec_cfg hfc_preccfg_pcie;

	const struct rtw89_dle_size wde_size0;

	const struct rtw89_dle_size wde_size4;

	const struct rtw89_dle_size wde_size6;

	const struct rtw89_dle_size wde_size9;

	const struct rtw89_dle_size wde_size18;

	const struct rtw89_dle_size wde_size19;

	const struct rtw89_dle_size ple_size0;

	const struct rtw89_dle_size ple_size4;

	const struct rtw89_dle_size ple_size6;

	const struct rtw89_dle_size ple_size8;

	const struct rtw89_dle_size ple_size18;

	const struct rtw89_dle_size ple_size19;

	const struct rtw89_wde_quota wde_qt0;

	const struct rtw89_wde_quota wde_qt4;

	const struct rtw89_wde_quota wde_qt6;

	const struct rtw89_wde_quota wde_qt17;

	const struct rtw89_wde_quota wde_qt18;

	const struct rtw89_ple_quota ple_qt4;

	const struct rtw89_ple_quota ple_qt5;

	const struct rtw89_ple_quota ple_qt13;

	const struct rtw89_ple_quota ple_qt18;

	const struct rtw89_ple_quota ple_qt44;

	const struct rtw89_ple_quota ple_qt45;

	const struct rtw89_ple_quota ple_qt46;

	const struct rtw89_ple_quota ple_qt47;

	const struct rtw89_ple_quota ple_qt58;

};



extern const struct rtw89_mac_size_set rtw89_mac_size;

drivers/net/wireless/realtek/rtw89/rtw8852b.c

+14 −0
Original line number Diff line number Diff line
@@ -6,6 +6,19 @@ 
#include "mac.h"

#include "reg.h"



static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = {

	[RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6,

			   &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,

			   &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,

			   &rtw89_mac_size.ple_qt58},

	[RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,

			    &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,

			    &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,

			    &rtw89_mac_size.ple_qt13},

	[RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,

			       NULL},

};



static int rtw8852b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)

{

	int ret;
@@ -68,6 +81,7 @@ const struct rtw89_chip_info rtw8852b_chip_info = { 
	.chip_id		= RTL8852B,

	.fifo_size		= 196608,

	.dle_scc_rsvd_size	= 98304,

	.dle_mem		= rtw8852b_dle_mem_pcie,

	.dma_ch_mask		= BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |

				  BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |

				  BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),