Commit a81de4a2 authored by Hamza Mahfooz's avatar Hamza Mahfooz Committed by Alex Deucher
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Revert "drm/amd/display: Remove v_startup workaround for dcn3+" 

This reverts commit 3a31e8b8.

We still need to call dcn20_adjust_freesync_v_startup() for older DCN3+
ASICs. Otherwise, it can cause DP to HDMI 2.1 PCONs to fail to light up.

Cc: stable@vger.kernel.org
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2809


Reviewed-by: default avatarFangzhi Zuo <jerry.zuo@amd.com>
Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 35588314

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

+4 −20
Original line number Diff line number Diff line
@@ -1099,6 +1099,10 @@ void dcn20_calculate_dlg_params(struct dc *dc, 
		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =

						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)

			dcn20_adjust_freesync_v_startup(

				&context->res_ctx.pipe_ctx[i].stream->timing,

				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);



		pipe_idx++;

	}
@@ -1927,7 +1931,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co 
	int vlevel = 0;

	int pipe_split_from[MAX_PIPES];

	int pipe_cnt = 0;

	int i = 0;

	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);

	DC_LOGGER_INIT(dc->ctx->logger);
@@ -1951,15 +1954,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co 
	dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);

	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		if (!context->res_ctx.pipe_ctx[i].stream)

			continue;

		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)

			dcn20_adjust_freesync_v_startup(

				&context->res_ctx.pipe_ctx[i].stream->timing,

				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);

	}



	BW_VAL_TRACE_END_WATERMARKS();



	goto validate_out;
@@ -2232,7 +2226,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, 
	int vlevel = 0;

	int pipe_split_from[MAX_PIPES];

	int pipe_cnt = 0;

	int i = 0;

	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);

	DC_LOGGER_INIT(dc->ctx->logger);
@@ -2261,15 +2254,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, 
	dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);

	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		if (!context->res_ctx.pipe_ctx[i].stream)

			continue;

		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)

			dcn20_adjust_freesync_v_startup(

				&context->res_ctx.pipe_ctx[i].stream->timing,

				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);

	}



	BW_VAL_TRACE_END_WATERMARKS();



	goto validate_out;