Commit 3a31e8b8 authored by Daniel Miess's avatar Daniel Miess Committed by Alex Deucher
Browse files

drm/amd/display: Remove v_startup workaround for dcn3+ 



[Why]
Calls to dcn20_adjust_freesync_v_startup are no longer
needed as of dcn3+ and can cause underflow in some cases

[How]
Move calls to dcn20_adjust_freesync_v_startup up into
validate_bandwidth for dcn2.x

Reviewed-by: default avatarJun Lei <jun.lei@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarDaniel Miess <daniel.miess@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 50a32b8c

drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c

+20 −4
Original line number Diff line number Diff line
@@ -1099,10 +1099,6 @@ void dcn20_calculate_dlg_params(struct dc *dc, 
		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =

						pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;

		context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;

		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)

			dcn20_adjust_freesync_v_startup(

				&context->res_ctx.pipe_ctx[i].stream->timing,

				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);



		pipe_idx++;

	}
@@ -1931,6 +1927,7 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co 
	int vlevel = 0;

	int pipe_split_from[MAX_PIPES];

	int pipe_cnt = 0;

	int i = 0;

	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);

	DC_LOGGER_INIT(dc->ctx->logger);
@@ -1954,6 +1951,15 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co 
	dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);

	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		if (!context->res_ctx.pipe_ctx[i].stream)

			continue;

		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)

			dcn20_adjust_freesync_v_startup(

				&context->res_ctx.pipe_ctx[i].stream->timing,

				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);

	}



	BW_VAL_TRACE_END_WATERMARKS();



	goto validate_out;
@@ -2226,6 +2232,7 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, 
	int vlevel = 0;

	int pipe_split_from[MAX_PIPES];

	int pipe_cnt = 0;

	int i = 0;

	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);

	DC_LOGGER_INIT(dc->ctx->logger);
@@ -2254,6 +2261,15 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, 
	dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);

	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		if (!context->res_ctx.pipe_ctx[i].stream)

			continue;

		if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)

			dcn20_adjust_freesync_v_startup(

				&context->res_ctx.pipe_ctx[i].stream->timing,

				&context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);

	}



	BW_VAL_TRACE_END_WATERMARKS();



	goto validate_out;