Commit a48fa7ef authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-next-2023-09-08' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regular rounds of rc1 fixes, a large bunch for amdgpu since it's three
  weeks in one go, one i915, one nouveau and one ivpu.

  I think there might be a few more fixes in misc that I haven't pulled
  in yet, but we should get them all for rc2.

  amdgpu:
   - Display replay fixes
   - Fixes for headless boards
   - Fix documentation breakage
   - RAS fixes
   - Handle newer IP discovery tables
   - SMU 13.0.6 fixes
   - SR-IOV fixes
   - Display vstartup fixes
   - NBIO 7.9 fixes
   - Display scaling mode fixes
   - Debugfs power reporting fix
   - GC 9.4.3 fixes
   - Dirty framebuffer fixes for fbcon
   - eDP fixes
   - DCN 3.1.5 fix
   - Display ODM fixes
   - GPU core dump fix
   - Re-enable zops property now that IGT test is fixed
   - Fix possible UAF in CS code
   - Cursor degamma fix

  amdkfd:
   - HMM fixes
   - Interrupt masking fix
   - GFX11 MQD fixes

  i915:
   - Mark requests for GuC virtual engines to avoid use-after-free

  nouveau:
   - Fix fence state in nouveau_fence_emit()

  ivpu:
   - replace strncpy"

* tag 'drm-next-2023-09-08' of git://anongit.freedesktop.org/drm/drm: (51 commits)
  drm/amdgpu: Restrict bootloader wait to SMUv13.0.6
  drm/amd/display: prevent potential division by zero errors
  drm/amd/display: enable cursor degamma for DCN3+ DRM legacy gamma
  drm/amd/display: limit the v_startup workaround to ASICs older than DCN3.1
  Revert "drm/amd/display: Remove v_startup workaround for dcn3+"
  drm/amdgpu: fix amdgpu_cs_p1_user_fence
  Revert "Revert "drm/amd/display: Implement zpos property""
  drm/amdkfd: Add missing gfx11 MQD manager callbacks
  drm/amdgpu: Free ras cmd input buffer properly
  drm/amdgpu: Hide xcp partition sysfs under SRIOV
  drm/amdgpu: use read-modify-write mode for gfx v9_4_3 SQ setting
  drm/amdkfd: use mask to get v9 interrupt sq data bits correctly
  drm/amdgpu: Allocate coredump memory in a nonblocking way
  drm/amdgpu: Support query ecc cap for aqua_vanjaram
  drm/amdgpu: Add umc_info v4_0 structure
  drm/amd/display: always switch off ODM before committing more streams
  drm/amd/display: Remove wait while locked
  drm/amd/display: update blank state on ODM changes
  drm/amd/display: Add smu write msg id fail retry process
  drm/amdgpu: Add SMU v13.0.6 default reset methods
  ...
parents 73be7fb1 43ffcd6f

Documentation/gpu/amdgpu/driver-misc.rst

+4 −4
Original line number Diff line number Diff line
@@ -11,19 +11,19 @@ via sysfs 
product_name

------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c

   :doc: product_name



product_number

--------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   :doc: product_name

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c

   :doc: product_number



serial_number

-------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c

   :doc: serial_number



unique_id

drivers/accel/ivpu/ivpu_jsm_msg.c

+1 −2
Original line number Diff line number Diff line
@@ -118,8 +118,7 @@ int ivpu_jsm_dyndbg_control(struct ivpu_device *vdev, char *command, size_t size 
	struct vpu_jsm_msg resp;

	int ret;



	if (!strncpy(req.payload.dyndbg_control.dyndbg_cmd, command, VPU_DYNDBG_CMD_MAX_LEN - 1))

		return -ENOMEM;

	strscpy(req.payload.dyndbg_control.dyndbg_cmd, command, VPU_DYNDBG_CMD_MAX_LEN);



	ret = ivpu_ipc_send_receive(vdev, &req, VPU_JSM_MSG_DYNDBG_CONTROL_RSP, &resp,

				    VPU_IPC_CHAN_ASYNC_CMD, vdev->timeout.jsm);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+2 −6
Original line number Diff line number Diff line
@@ -442,9 +442,7 @@ void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 
			mem_info->local_mem_size_public,

			mem_info->local_mem_size_private);



	if (amdgpu_sriov_vf(adev))

		mem_info->mem_clk_max = adev->clock.default_mclk / 100;

	else if (adev->pm.dpm_enabled) {

	if (adev->pm.dpm_enabled) {

		if (amdgpu_emu_mode == 1)

			mem_info->mem_clk_max = 0;

		else
@@ -463,9 +461,7 @@ uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev) 
uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev)

{

	/* the sclk is in quantas of 10kHz */

	if (amdgpu_sriov_vf(adev))

		return adev->clock.default_sclk / 100;

	else if (adev->pm.dpm_enabled)

	if (adev->pm.dpm_enabled)

		return amdgpu_dpm_get_sclk(adev, false) / 100;

	else

		return 100;

drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

+16 −2
Original line number Diff line number Diff line
@@ -217,6 +217,7 @@ union umc_info { 
	struct atom_umc_info_v3_1 v31;

	struct atom_umc_info_v3_2 v32;

	struct atom_umc_info_v3_3 v33;

	struct atom_umc_info_v4_0 v40;

};



union vram_info {
@@ -508,9 +509,8 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev) 


	if (amdgpu_atom_parse_data_header(mode_info->atom_context,

				index, &size, &frev, &crev, &data_offset)) {

		umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset);

		if (frev == 3) {

			umc_info = (union umc_info *)

				(mode_info->atom_context->bios + data_offset);

			switch (crev) {

			case 1:

				umc_config = le32_to_cpu(umc_info->v31.umc_config);
@@ -533,6 +533,20 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev) 
				/* unsupported crev */

				return false;

			}

		} else if (frev == 4) {

			switch (crev) {

			case 0:

				umc_config1 = le32_to_cpu(umc_info->v40.umc_config1);

				ecc_default_enabled =

					(umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false;

				break;

			default:

				/* unsupported crev */

				return false;

			}

		} else {

			/* unsupported frev */

			return false;

		}

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+4 −14
Original line number Diff line number Diff line
@@ -127,7 +127,6 @@ static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p, 
{

	struct drm_gem_object *gobj;

	unsigned long size;

	int r;



	gobj = drm_gem_object_lookup(p->filp, data->handle);

	if (gobj == NULL)
@@ -137,23 +136,14 @@ static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p, 
	drm_gem_object_put(gobj);



	size = amdgpu_bo_size(p->uf_bo);

	if (size != PAGE_SIZE || (data->offset + 8) > size) {

		r = -EINVAL;

		goto error_unref;

	}

	if (size != PAGE_SIZE || data->offset > (size - 8))

		return -EINVAL;



	if (amdgpu_ttm_tt_get_usermm(p->uf_bo->tbo.ttm)) {

		r = -EINVAL;

		goto error_unref;

	}

	if (amdgpu_ttm_tt_get_usermm(p->uf_bo->tbo.ttm))

		return -EINVAL;



	*offset = data->offset;



	return 0;



error_unref:

	amdgpu_bo_unref(&p->uf_bo);

	return r;

}



static int amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser *p,