Loading drivers/ata/sata_mv.c +38 −38 Original line number Diff line number Diff line Loading @@ -1248,42 +1248,43 @@ static int mv_stop_edma(struct ata_port *ap) return err; } #ifdef ATA_DEBUG static void mv_dump_mem(void __iomem *start, unsigned bytes) static void mv_dump_mem(struct device *dev, void __iomem *start, unsigned bytes) { int b, w; int b, w, o; unsigned char linebuf[38]; for (b = 0; b < bytes; ) { DPRINTK("%p: ", start + b); for (w = 0; b < bytes && w < 4; w++) { printk("%08x ", readl(start + b)); for (w = 0, o = 0; b < bytes && w < 4; w++) { o += snprintf(linebuf + o, sizeof(linebuf) - o, "%08x ", readl(start + b)); b += sizeof(u32); } printk("\n"); dev_dbg(dev, "%s: %p: %s\n", __func__, start + b, linebuf); } } #endif #if defined(ATA_DEBUG) || defined(CONFIG_PCI) static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) { #ifdef ATA_DEBUG int b, w; u32 dw; int b, w, o; u32 dw = 0; unsigned char linebuf[38]; for (b = 0; b < bytes; ) { DPRINTK("%02x: ", b); for (w = 0; b < bytes && w < 4; w++) { for (w = 0, o = 0; b < bytes && w < 4; w++) { (void) pci_read_config_dword(pdev, b, &dw); printk("%08x ", dw); o += snprintf(linebuf + o, sizeof(linebuf) - o, "%08x ", dw); b += sizeof(u32); } printk("\n"); dev_dbg(&pdev->dev, "%s: %02x: %s\n", __func__, b, linebuf); } #endif } #endif static void mv_dump_all_regs(void __iomem *mmio_base, struct pci_dev *pdev) { #ifdef ATA_DEBUG void __iomem *hc_base; void __iomem *port_base; int start_port, num_ports, p, start_hc, num_hcs, hc; Loading @@ -1291,31 +1292,30 @@ static void mv_dump_all_regs(void __iomem *mmio_base, start_hc = start_port = 0; num_ports = 8; /* should be benign for 4 port devs */ num_hcs = 2; DPRINTK("All registers for port(s) %u-%u:\n", start_port, num_ports > 1 ? num_ports - 1 : start_port); dev_dbg(&pdev->dev, "%s: All registers for port(s) %u-%u:\n", __func__, start_port, num_ports > 1 ? num_ports - 1 : start_port); if (NULL != pdev) { DPRINTK("PCI config space regs:\n"); dev_dbg(&pdev->dev, "%s: PCI config space regs:\n", __func__); mv_dump_pci_cfg(pdev, 0x68); } DPRINTK("PCI regs:\n"); mv_dump_mem(mmio_base+0xc00, 0x3c); mv_dump_mem(mmio_base+0xd00, 0x34); mv_dump_mem(mmio_base+0xf00, 0x4); mv_dump_mem(mmio_base+0x1d00, 0x6c); dev_dbg(&pdev->dev, "%s: PCI regs:\n", __func__); mv_dump_mem(&pdev->dev, mmio_base+0xc00, 0x3c); mv_dump_mem(&pdev->dev, mmio_base+0xd00, 0x34); mv_dump_mem(&pdev->dev, mmio_base+0xf00, 0x4); mv_dump_mem(&pdev->dev, mmio_base+0x1d00, 0x6c); for (hc = start_hc; hc < start_hc + num_hcs; hc++) { hc_base = mv_hc_base(mmio_base, hc); DPRINTK("HC regs (HC %i):\n", hc); mv_dump_mem(hc_base, 0x1c); dev_dbg(&pdev->dev, "%s: HC regs (HC %i):\n", __func__, hc); mv_dump_mem(&pdev->dev, hc_base, 0x1c); } for (p = start_port; p < start_port + num_ports; p++) { port_base = mv_port_base(mmio_base, p); DPRINTK("EDMA regs (port %i):\n", p); mv_dump_mem(port_base, 0x54); DPRINTK("SATA regs (port %i):\n", p); mv_dump_mem(port_base+0x300, 0x60); dev_dbg(&pdev->dev, "%s: EDMA regs (port %i):\n", __func__, p); mv_dump_mem(&pdev->dev, port_base, 0x54); dev_dbg(&pdev->dev, "%s: SATA regs (port %i):\n", __func__, p); mv_dump_mem(&pdev->dev, port_base+0x300, 0x60); } #endif } static unsigned int mv_scr_offset(unsigned int sc_reg_in) Loading Loading @@ -2955,7 +2955,7 @@ static int mv_pci_error(struct ata_host *host, void __iomem *mmio) dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause); DPRINTK("All regs @ PCI error\n"); dev_dbg(host->dev, "%s: All regs @ PCI error\n", __func__); mv_dump_all_regs(mmio, to_pci_dev(host->dev)); writelfl(0, mmio + hpriv->irq_cause_offset); Loading Loading
drivers/ata/sata_mv.c +38 −38 Original line number Diff line number Diff line Loading @@ -1248,42 +1248,43 @@ static int mv_stop_edma(struct ata_port *ap) return err; } #ifdef ATA_DEBUG static void mv_dump_mem(void __iomem *start, unsigned bytes) static void mv_dump_mem(struct device *dev, void __iomem *start, unsigned bytes) { int b, w; int b, w, o; unsigned char linebuf[38]; for (b = 0; b < bytes; ) { DPRINTK("%p: ", start + b); for (w = 0; b < bytes && w < 4; w++) { printk("%08x ", readl(start + b)); for (w = 0, o = 0; b < bytes && w < 4; w++) { o += snprintf(linebuf + o, sizeof(linebuf) - o, "%08x ", readl(start + b)); b += sizeof(u32); } printk("\n"); dev_dbg(dev, "%s: %p: %s\n", __func__, start + b, linebuf); } } #endif #if defined(ATA_DEBUG) || defined(CONFIG_PCI) static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) { #ifdef ATA_DEBUG int b, w; u32 dw; int b, w, o; u32 dw = 0; unsigned char linebuf[38]; for (b = 0; b < bytes; ) { DPRINTK("%02x: ", b); for (w = 0; b < bytes && w < 4; w++) { for (w = 0, o = 0; b < bytes && w < 4; w++) { (void) pci_read_config_dword(pdev, b, &dw); printk("%08x ", dw); o += snprintf(linebuf + o, sizeof(linebuf) - o, "%08x ", dw); b += sizeof(u32); } printk("\n"); dev_dbg(&pdev->dev, "%s: %02x: %s\n", __func__, b, linebuf); } #endif } #endif static void mv_dump_all_regs(void __iomem *mmio_base, struct pci_dev *pdev) { #ifdef ATA_DEBUG void __iomem *hc_base; void __iomem *port_base; int start_port, num_ports, p, start_hc, num_hcs, hc; Loading @@ -1291,31 +1292,30 @@ static void mv_dump_all_regs(void __iomem *mmio_base, start_hc = start_port = 0; num_ports = 8; /* should be benign for 4 port devs */ num_hcs = 2; DPRINTK("All registers for port(s) %u-%u:\n", start_port, num_ports > 1 ? num_ports - 1 : start_port); dev_dbg(&pdev->dev, "%s: All registers for port(s) %u-%u:\n", __func__, start_port, num_ports > 1 ? num_ports - 1 : start_port); if (NULL != pdev) { DPRINTK("PCI config space regs:\n"); dev_dbg(&pdev->dev, "%s: PCI config space regs:\n", __func__); mv_dump_pci_cfg(pdev, 0x68); } DPRINTK("PCI regs:\n"); mv_dump_mem(mmio_base+0xc00, 0x3c); mv_dump_mem(mmio_base+0xd00, 0x34); mv_dump_mem(mmio_base+0xf00, 0x4); mv_dump_mem(mmio_base+0x1d00, 0x6c); dev_dbg(&pdev->dev, "%s: PCI regs:\n", __func__); mv_dump_mem(&pdev->dev, mmio_base+0xc00, 0x3c); mv_dump_mem(&pdev->dev, mmio_base+0xd00, 0x34); mv_dump_mem(&pdev->dev, mmio_base+0xf00, 0x4); mv_dump_mem(&pdev->dev, mmio_base+0x1d00, 0x6c); for (hc = start_hc; hc < start_hc + num_hcs; hc++) { hc_base = mv_hc_base(mmio_base, hc); DPRINTK("HC regs (HC %i):\n", hc); mv_dump_mem(hc_base, 0x1c); dev_dbg(&pdev->dev, "%s: HC regs (HC %i):\n", __func__, hc); mv_dump_mem(&pdev->dev, hc_base, 0x1c); } for (p = start_port; p < start_port + num_ports; p++) { port_base = mv_port_base(mmio_base, p); DPRINTK("EDMA regs (port %i):\n", p); mv_dump_mem(port_base, 0x54); DPRINTK("SATA regs (port %i):\n", p); mv_dump_mem(port_base+0x300, 0x60); dev_dbg(&pdev->dev, "%s: EDMA regs (port %i):\n", __func__, p); mv_dump_mem(&pdev->dev, port_base, 0x54); dev_dbg(&pdev->dev, "%s: SATA regs (port %i):\n", __func__, p); mv_dump_mem(&pdev->dev, port_base+0x300, 0x60); } #endif } static unsigned int mv_scr_offset(unsigned int sc_reg_in) Loading Loading @@ -2955,7 +2955,7 @@ static int mv_pci_error(struct ata_host *host, void __iomem *mmio) dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause); DPRINTK("All regs @ PCI error\n"); dev_dbg(host->dev, "%s: All regs @ PCI error\n", __func__); mv_dump_all_regs(mmio, to_pci_dev(host->dev)); writelfl(0, mmio + hpriv->irq_cause_offset); Loading