Commit a0bc8ae5 authored by Rex-BC Chen's avatar Rex-BC Chen Committed by Stephen Boyd
Browse files

clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195 



The infra_ao reset is needed for MT8192 and MT8195.
- Add mtk_clk_rst_desc for MT8192 and MT8195
- Add register reset controller function for MT8192 infra_ao.
- Move definition of infra reset from cl-mt8183.c to reset.h
  because it's the same definition with MT8192 and MT8195.
- Add new definition of infra reset_4 for MT8192 and MT8195.
- Add infra_ao_idx_map for MT8192 and MT8195.

Signed-off-by: default avatarRex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
[Nícolas: Test for MT8192]
Tested-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220523093346.28493-15-rex-bc.chen@mediatek.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent fb91526b

drivers/clk/mediatek/clk-mt8183.c

+0 −6
Original line number Diff line number Diff line
@@ -18,12 +18,6 @@ 


#include <dt-bindings/clock/mt8183-clk.h>



/* Infra global controller reset set register */

#define INFRA_RST0_SET_OFFSET		0x120

#define INFRA_RST1_SET_OFFSET		0x130

#define INFRA_RST2_SET_OFFSET		0x140

#define INFRA_RST3_SET_OFFSET		0x150



static DEFINE_SPINLOCK(mt8183_clk_lock);



static const struct mtk_fixed_clk top_fixed_clks[] = {

drivers/clk/mediatek/clk-mt8192.c

+29 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include "clk-pll.h"



#include <dt-bindings/clock/mt8192-clk.h>

#include <dt-bindings/reset/mt8192-resets.h>



static DEFINE_SPINLOCK(mt8192_clk_lock);
@@ -1114,6 +1115,30 @@ static const struct mtk_gate top_clks[] = { 
	GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25),

};



static u16 infra_ao_rst_ofs[] = {

	INFRA_RST0_SET_OFFSET,

	INFRA_RST1_SET_OFFSET,

	INFRA_RST2_SET_OFFSET,

	INFRA_RST3_SET_OFFSET,

	INFRA_RST4_SET_OFFSET,

};



static u16 infra_ao_idx_map[] = {

	[MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,

	[MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15,

	[MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,

	[MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1,

	[MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12,

};



static const struct mtk_clk_rst_desc clk_rst_desc = {

	.version = MTK_RST_SET_CLR,

	.rst_bank_ofs = infra_ao_rst_ofs,

	.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),

	.rst_idx_map = infra_ao_idx_map,

	.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),

};



#define MT8192_PLL_FMAX		(3800UL * MHZ)

#define MT8192_PLL_FMIN		(1500UL * MHZ)

#define MT8192_INTEGER_BITS	8
@@ -1240,6 +1265,10 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev) 
	if (r)

		goto free_clk_data;



	r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);

	if (r)

		goto free_clk_data;



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

	if (r)

		goto free_clk_data;

drivers/clk/mediatek/clk-mt8195-infra_ao.c

+24 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include "clk-mtk.h"



#include <dt-bindings/clock/mt8195-clk.h>

#include <dt-bindings/reset/mt8195-resets.h>

#include <linux/clk-provider.h>

#include <linux/platform_device.h>
@@ -182,9 +183,32 @@ static const struct mtk_gate infra_ao_clks[] = { 
	GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),

};



static u16 infra_ao_rst_ofs[] = {

	INFRA_RST0_SET_OFFSET,

	INFRA_RST1_SET_OFFSET,

	INFRA_RST2_SET_OFFSET,

	INFRA_RST3_SET_OFFSET,

	INFRA_RST4_SET_OFFSET,

};



static u16 infra_ao_idx_map[] = {

	[MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,

	[MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,

	[MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10,

};



static struct mtk_clk_rst_desc infra_ao_rst_desc = {

	.version = MTK_RST_SET_CLR,

	.rst_bank_ofs = infra_ao_rst_ofs,

	.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),

	.rst_idx_map = infra_ao_idx_map,

	.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),

};



static const struct mtk_clk_desc infra_ao_desc = {

	.clks = infra_ao_clks,

	.num_clks = ARRAY_SIZE(infra_ao_clks),

	.rst_desc = &infra_ao_rst_desc,

};



static const struct of_device_id of_match_clk_mt8195_infra_ao[] = {

drivers/clk/mediatek/reset.h

+7 −0
Original line number Diff line number Diff line
@@ -11,6 +11,13 @@ 


#define RST_NR_PER_BANK 32



/* Infra global controller reset set register */

#define INFRA_RST0_SET_OFFSET 0x120

#define INFRA_RST1_SET_OFFSET 0x130

#define INFRA_RST2_SET_OFFSET 0x140

#define INFRA_RST3_SET_OFFSET 0x150

#define INFRA_RST4_SET_OFFSET 0x730



/**

 * enum mtk_reset_version - Version of MediaTek clock reset controller.

 * @MTK_RST_SIMPLE: Use the same registers for bit set and clear.