Commit fb91526b authored by Rex-BC Chen's avatar Rex-BC Chen Committed by Stephen Boyd
Browse files

dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195 



To support reset of infra_ao, add the index of infra_ao reset of
thermal/svs/pcei for MT8192 and thermal/svs for MT8195.

Signed-off-by: default avatarRex-BC Chen <rex-bc.chen@mediatek.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
[Nícolas: Test for MT8192]
Tested-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220523093346.28493-14-rex-bc.chen@mediatek.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 4d352eb9

include/dt-bindings/reset/mt8192-resets.h

+8 −0
Original line number Original line Diff line number Diff line
@@ -7,6 +7,7 @@ 
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192

#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192

#define _DT_BINDINGS_RESET_CONTROLLER_MT8192

#define _DT_BINDINGS_RESET_CONTROLLER_MT8192





/* TOPRGU resets */

#define MT8192_TOPRGU_MM_SW_RST					1

#define MT8192_TOPRGU_MM_SW_RST					1

#define MT8192_TOPRGU_MFG_SW_RST				2

#define MT8192_TOPRGU_MFG_SW_RST				2

#define MT8192_TOPRGU_VENC_SW_RST				3

#define MT8192_TOPRGU_VENC_SW_RST				3
@@ -30,4 +31,11 @@ 
/* MMSYS resets */

/* MMSYS resets */

#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15

#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0			15





/* INFRA resets */

#define MT8192_INFRA_RST0_THERM_CTRL_SWRST		0

#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST		1

#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST	2

#define MT8192_INFRA_RST4_PCIE_TOP_SWRST		3

#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST	4



#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
 
#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */

include/dt-bindings/reset/mt8195-resets.h

+6 −0
Original line number Original line Diff line number Diff line
@@ -7,6 +7,7 @@ 
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195

#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195

#define _DT_BINDINGS_RESET_CONTROLLER_MT8195

#define _DT_BINDINGS_RESET_CONTROLLER_MT8195





/* TOPRGU resets */

#define MT8195_TOPRGU_CONN_MCU_SW_RST          0

#define MT8195_TOPRGU_CONN_MCU_SW_RST          0

#define MT8195_TOPRGU_INFRA_GRST_SW_RST        1

#define MT8195_TOPRGU_INFRA_GRST_SW_RST        1

#define MT8195_TOPRGU_APU_SW_RST               2

#define MT8195_TOPRGU_APU_SW_RST               2
@@ -26,4 +27,9 @@ 




#define MT8195_TOPRGU_SW_RST_NUM               16

#define MT8195_TOPRGU_SW_RST_NUM               16





/* INFRA resets */

#define MT8195_INFRA_RST0_THERM_CTRL_SWRST     0

#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1

#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2



#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
 
#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */