Commit 9e94ff33 authored by Alex Sierra's avatar Alex Sierra Committed by Alex Deucher
Browse files

drm/amdgpu: reroute VMC and UMD to IH ring 1 for oss v5 



[Why]
Due Page faults can easily overwhelm the interrupt handler.
So to make sure that we never lose valuable interrupts on the primary ring
we re-route page faults to IH ring 1.
It also facilitates the recovery page process, since it's already
running from a process context.
This is valid for Arcturus and future Navi generation GPUs.

[How]
Setting IH_CLIENT_CFG_DATA for VMC and UMD IH clients.

Signed-off-by: default avatarAlex Sierra <alex.sierra@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0ab176e6

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

+19 −0
Original line number Diff line number Diff line
@@ -205,6 +205,24 @@ static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) 
	return ih_doorbell_rtpr;

}



static void navi10_ih_reroute_ih(struct amdgpu_device *adev)

{

	uint32_t tmp;



	/* Reroute to IH ring 1 for VMC */

	WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12);

	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);

	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);

	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);

	WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);



	/* Reroute IH ring 1 for UMC */

	WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B);

	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);

	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);

	WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);

}



/**

 * navi10_ih_irq_init - init and enable the interrupt ring

 *
@@ -243,6 +261,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev) 
	} else {

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

	}

	navi10_ih_reroute_ih(adev);



	if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {

		if (ih->use_bus_addr) {