Commit 0ab176e6 authored by Alex Sierra's avatar Alex Sierra Committed by Alex Deucher
Browse files

drm/amdgpu: call psp to program ih cntl in SR-IOV for Navi 



call psp to program ih cntl in SR-IOV if supported on Navi and Arcturus.

Signed-off-by: default avatarAlex Sierra <alex.sierra@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ab518012

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

+80 −10
Original line number Diff line number Diff line
@@ -49,14 +49,30 @@ static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 


	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);

	if (amdgpu_sriov_vf(adev)) {

		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {

			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");

			return;

		}

	} else {

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

	}



	adev->irq.ih.enabled = true;



	if (adev->irq.ih1.ring_size) {

		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);

		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,

					   RB_ENABLE, 1);

		if (amdgpu_sriov_vf(adev)) {

			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,

						ih_rb_cntl)) {

				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");

				return;

			}

		} else {

			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);

		}

		adev->irq.ih1.enabled = true;

	}
@@ -64,7 +80,15 @@ static void navi10_ih_enable_interrupts(struct amdgpu_device *adev) 
		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);

		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,

					   RB_ENABLE, 1);

		if (amdgpu_sriov_vf(adev)) {

			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,

						ih_rb_cntl)) {

				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");

				return;

			}

		} else {

			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);

		}

		adev->irq.ih2.enabled = true;

	}

}
@@ -82,7 +106,15 @@ static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 


	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);

	if (amdgpu_sriov_vf(adev)) {

		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {

			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");

			return;

		}

	} else {

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

	}



	/* set rptr, wptr to 0 */

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
@@ -93,7 +125,15 @@ static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 
		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);

		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,

					   RB_ENABLE, 0);

		if (amdgpu_sriov_vf(adev)) {

			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,

						ih_rb_cntl)) {

				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");

				return;

			}

		} else {

			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);

		}

		/* set rptr, wptr to 0 */

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);
@@ -105,7 +145,15 @@ static void navi10_ih_disable_interrupts(struct amdgpu_device *adev) 
		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);

		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING2,

					   RB_ENABLE, 0);

		if (amdgpu_sriov_vf(adev)) {

			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,

						ih_rb_cntl)) {

				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");

				return;

			}

		} else {

			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);

		}

		/* set rptr, wptr to 0 */

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);
@@ -187,6 +235,14 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev) 
	ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl);

	ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM,

				   !!adev->irq.msi_enabled);

	if (amdgpu_sriov_vf(adev)) {

		if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, ih_rb_cntl)) {

			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");

			return -ETIMEDOUT;

		}

	} else {

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

	}



	if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {

		if (ih->use_bus_addr) {
@@ -197,8 +253,6 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev) 
		}

	}



	WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);



	/* set the writeback address whether it's enabled or not */

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,

		     lower_32_bits(ih->wptr_addr));
@@ -227,7 +281,15 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev) 
					   WPTR_OVERFLOW_ENABLE, 0);

		ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

					   RB_FULL_DRAIN_ENABLE, 1);

		if (amdgpu_sriov_vf(adev)) {

			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1,

						ih_rb_cntl)) {

				DRM_ERROR("program IH_RB_CNTL_RING1 failed!\n");

				return -ETIMEDOUT;

			}

		} else {

			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);

		}

		/* set rptr, wptr to 0 */

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);
@@ -245,7 +307,15 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev) 
		ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2);

		ih_rb_cntl = navi10_ih_rb_cntl(ih, ih_rb_cntl);



		if (amdgpu_sriov_vf(adev)) {

			if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING2,

						ih_rb_cntl)) {

				DRM_ERROR("program IH_RB_CNTL_RING2 failed!\n");

				return -ETIMEDOUT;

			}

		} else {

			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);

		}

		/* set rptr, wptr to 0 */

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);

		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);