Commit 9e1ab1fe authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.1-tag1' of... 

Merge tag 'renesas-clk-for-v6.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8
  - Add I2C clocks and resets on RZ/V2M
  - Document clock support for the RZ/Five SoC
  - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC
  clk: renesas: r8a779f0: Add MSIOF clocks
  clk: renesas: r9a09g011: Add IIC clock and reset entries
  clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info
  clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks
  clk: renesas: r8a779f0: Add CMT clocks
  clk: renesas: r8a779f0: Add SDH0 clock
parents 568035b0 e312ae92

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ description: | 
properties:

  compatible:

    enum:

      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}

      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five

      - renesas,r9a07g044-cpg # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg # RZ/V2L

      - renesas,r9a09g011-cpg # RZ/V2M

drivers/clk/renesas/r8a779f0-cpg-mssr.c

+20 −1
Original line number Diff line number Diff line
@@ -108,7 +108,13 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = { 
	DEF_FIXED("cbfusa",	R8A779F0_CLK_CBFUSA,	CLK_EXTAL,	2, 1),

	DEF_FIXED("cpex",	R8A779F0_CLK_CPEX,	CLK_EXTAL,	2, 1),



	DEF_GEN4_SD("sd0",	R8A779F0_CLK_SD0,	CLK_SDSRC,	0x870),

	DEF_FIXED("sasyncrt",	R8A779F0_CLK_SASYNCRT,	CLK_PLL5_DIV4,	48, 1),

	DEF_FIXED("sasyncperd1", R8A779F0_CLK_SASYNCPERD1, CLK_PLL5_DIV4, 3, 1),

	DEF_FIXED("sasyncperd2", R8A779F0_CLK_SASYNCPERD2, R8A779F0_CLK_SASYNCPERD1, 2, 1),

	DEF_FIXED("sasyncperd4", R8A779F0_CLK_SASYNCPERD4, R8A779F0_CLK_SASYNCPERD1, 4, 1),



	DEF_GEN4_SDH("sdh0",	R8A779F0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SD("sd0",	R8A779F0_CLK_SD0,	R8A779F0_CLK_SD0H, 0x870),



	DEF_BASE("rpc",		R8A779F0_CLK_RPC,	CLK_TYPE_GEN4_RPC, CLK_RPCSRC),

	DEF_BASE("rpcd2",	R8A779F0_CLK_RPCD2,	CLK_TYPE_GEN4_RPCD2, R8A779F0_CLK_RPC),
@@ -130,6 +136,10 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { 
	DEF_MOD("i2c3",		521,	R8A779F0_CLK_S0D6_PER),

	DEF_MOD("i2c4",		522,	R8A779F0_CLK_S0D6_PER),

	DEF_MOD("i2c5",		523,	R8A779F0_CLK_S0D6_PER),

	DEF_MOD("msiof0",	618,	R8A779F0_CLK_MSO),

	DEF_MOD("msiof1",	619,	R8A779F0_CLK_MSO),

	DEF_MOD("msiof2",	620,	R8A779F0_CLK_MSO),

	DEF_MOD("msiof3",	621,	R8A779F0_CLK_MSO),

	DEF_MOD("pcie0",	624,	R8A779F0_CLK_S0D2),

	DEF_MOD("pcie1",	625,	R8A779F0_CLK_S0D2),

	DEF_MOD("scif0",	702,	R8A779F0_CLK_S0D12_PER),
@@ -139,7 +149,16 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { 
	DEF_MOD("sdhi0",        706,    R8A779F0_CLK_SD0),

	DEF_MOD("sys-dmac0",	709,	R8A779F0_CLK_S0D3_PER),

	DEF_MOD("sys-dmac1",	710,	R8A779F0_CLK_S0D3_PER),

	DEF_MOD("tmu0",		713,	R8A779F0_CLK_SASYNCRT),

	DEF_MOD("tmu1",		714,	R8A779F0_CLK_SASYNCPERD2),

	DEF_MOD("tmu2",		715,	R8A779F0_CLK_SASYNCPERD2),

	DEF_MOD("tmu3",		716,	R8A779F0_CLK_SASYNCPERD2),

	DEF_MOD("tmu4",		717,	R8A779F0_CLK_SASYNCPERD2),

	DEF_MOD("wdt",		907,	R8A779F0_CLK_R),

	DEF_MOD("cmt0",		910,	R8A779F0_CLK_R),

	DEF_MOD("cmt1",		911,	R8A779F0_CLK_R),

	DEF_MOD("cmt2",		912,	R8A779F0_CLK_R),

	DEF_MOD("cmt3",		913,	R8A779F0_CLK_R),

	DEF_MOD("pfc0",		915,	R8A779F0_CLK_CL16M),

	DEF_MOD("tsc",		919,	R8A779F0_CLK_CL16M),

	DEF_MOD("ufs",		1514,	R8A779F0_CLK_S0D4_HSC),

drivers/clk/renesas/r9a07g044-cpg.c

+2 −0
Original line number Diff line number Diff line
@@ -414,6 +414,7 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { 
	MOD_CLK_BASE + R9A07G044_DMAC_ACLK,

};



#ifdef CONFIG_CLK_R9A07G044

const struct rzg2l_cpg_info r9a07g044_cpg_info = {

	/* Core Clocks */

	.core_clks = core_clks.common,
@@ -436,6 +437,7 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { 


	.has_clk_mon_regs = true,

};

#endif



#ifdef CONFIG_CLK_R9A07G054

const struct rzg2l_cpg_info r9a07g054_cpg_info = {

drivers/clk/renesas/r9a09g011-cpg.c

+4 −0
Original line number Diff line number Diff line
@@ -132,6 +132,8 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { 
	DEF_COUPLED("eth_chi",	R9A09G011_ETH0_CLK_CHI,	 CLK_PLL2_100, 0x40c, 8),

	DEF_MOD("eth_clk_gptp",	R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),

	DEF_MOD("syc_cnt_clk",	R9A09G011_SYC_CNT_CLK,	 CLK_MAIN_24,  0x41c, 12),

	DEF_MOD("iic_pclk0",	R9A09G011_IIC_PCLK0,	 CLK_SEL_E,    0x420, 12),

	DEF_MOD("iic_pclk1",	R9A09G011_IIC_PCLK1,	 CLK_SEL_E,    0x424, 12),

	DEF_MOD("wdt0_pclk",	R9A09G011_WDT0_PCLK,	 CLK_SEL_E,    0x428, 12),

	DEF_MOD("wdt0_clk",	R9A09G011_WDT0_CLK,	 CLK_MAIN,     0x428, 13),

	DEF_MOD("urt_pclk",	R9A09G011_URT_PCLK,	 CLK_SEL_E,    0x438, 4),
@@ -143,6 +145,8 @@ static const struct rzg2l_reset r9a09g011_resets[] = { 
	DEF_RST(R9A09G011_PFC_PRESETN,		0x600, 2),

	DEF_RST_MON(R9A09G011_ETH0_RST_HW_N,	0x608, 11, 11),

	DEF_RST_MON(R9A09G011_SYC_RST_N,	0x610, 9,  13),

	DEF_RST(R9A09G011_IIC_GPA_PRESETN,	0x614, 8),

	DEF_RST(R9A09G011_IIC_GPB_PRESETN,	0x614, 9),

	DEF_RST_MON(R9A09G011_WDT0_PRESETN,	0x614, 12, 19),

};