Commit e312ae92 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC 



The CPG block on the RZ/Five SoC is almost identical to one found on the
RZ/G2UL SoC. "renesas,r9a07g043-cpg" compatible string will be used on
the RZ/Five SoC so to make this clear, update the comment to include
RZ/Five SoC.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 644814c1

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ description: | 
properties:

  compatible:

    enum:

      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}

      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five

      - renesas,r9a07g044-cpg # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg # RZ/V2L

      - renesas,r9a09g011-cpg # RZ/V2M