Commit 9d6b2041 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: convert sienna_cichlid_populate_umd_state_clk() to use IP version 



Rather than asic type.

Reviewed-by: default avatarGuchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2388a778

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+5 −5
Original line number Diff line number Diff line
@@ -1464,19 +1464,19 @@ static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) 
	pstate_table->socclk_pstate.min = soc_table->min;

	pstate_table->socclk_pstate.peak = soc_table->max;



	switch (adev->asic_type) {

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	switch (adev->ip_versions[MP1_HWIP][0]) {

	case IP_VERSION(11, 0, 7):

	case IP_VERSION(11, 0, 11):

		pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;

		pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;

		pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;

		break;

	case CHIP_DIMGREY_CAVEFISH:

	case IP_VERSION(11, 0, 12):

		pstate_table->gfxclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_GFXCLK;

		pstate_table->uclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_MEMCLK;

		pstate_table->socclk_pstate.standard = DIMGREY_CAVEFISH_UMD_PSTATE_PROFILING_SOCCLK;

		break;

	case CHIP_BEIGE_GOBY:

	case IP_VERSION(11, 0, 13):

		pstate_table->gfxclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_GFXCLK;

		pstate_table->uclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_MEMCLK;

		pstate_table->socclk_pstate.standard = BEIGE_GOBY_UMD_PSTATE_PROFILING_SOCCLK;