Commit 2388a778 authored by Fangzhi Zuo's avatar Fangzhi Zuo Committed by Alex Deucher
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drm/amd/display: Halve DTB Clock Value for DCN32 



VBIOS default clock value was halved, so the hardcoded dtb value should be
halved as well.

dtb clock should come from SMU eventually, but now dtb clock switching is not
fully supported yet in SMU.

Halve the dtb hardcoded value for now to have UHBR10 light up. Will rely on
SMU for dtb clock switching once available. The w/a is for DCN32 only, DCN321
should adopt the original value.

Signed-off-by: default avatarFangzhi Zuo <Jerry.Zuo@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3ccb9ea9

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+1 −1
Original line number Diff line number Diff line
@@ -599,7 +599,7 @@ void dcn32_clk_mgr_construct( 
	clk_mgr->dfs_ref_freq_khz = 100000;



	clk_mgr->base.dprefclk_khz = 717000; /* Changed as per DCN3.2_clock_frequency doc */

	clk_mgr->dccg->ref_dtbclk_khz = 477800;

	clk_mgr->dccg->ref_dtbclk_khz = 268750;



	/* integer part is now VCO frequency in kHz */

	clk_mgr->base.dentist_vco_freq_khz = 4300000;//dcn32_get_vco_frequency_from_reg(clk_mgr);