Commit 3ccb9ea9 authored by Dillon Varone's avatar Dillon Varone Committed by Alex Deucher
Browse files

drm/amd/display: Add additional guard for FCLK pstate message for DCN321 



Signed-off-by: default avatarDillon Varone <dillon.varone@amd.com>
Signed-off-by: default avatarFangzhi Zuo <Jerry.Zuo@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 72b5f23c

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+4 −3
Original line number Diff line number Diff line
@@ -346,8 +346,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, 
					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);

	}



	if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support) &&

			clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21) {

	if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 &&

			should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_state_change_support)) {

		clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support;



		/* To disable FCLK P-state switching, send FCLK_PSTATE_NOTSUPPORTED message to PMFW */
@@ -368,7 +368,8 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, 
			(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))

		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));



	if (clk_mgr_base->clks.fclk_p_state_change_support &&

	if (clk_mgr_base->ctx->dce_version != DCN_VERSION_3_21 &&

			clk_mgr_base->clks.fclk_p_state_change_support &&

			(update_uclk || !clk_mgr_base->clks.fclk_prev_p_state_change_support)) {

		/* Handle the code for sending a message to PMFW that FCLK P-state change is supported */

		dcn32_smu_send_fclk_pstate_message(clk_mgr, FCLK_PSTATE_SUPPORTED);