Commit 9ce5884e authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/display: Only keep PSR enabled if there is active planes 



PSR always had a requirement to only be enabled if there is active
planes but not following that never caused any issues.
But that changes in Alderlake-P, leaving PSR enabled without
active planes causes transcoder/port underruns.

Similar behavior was fixed during the pipe disable sequence by
commit 84030adb ("drm/i915/display: Disable audio, DRRS and PSR before planes").

intel_dp_compute_psr_vsc_sdp() had to move from
intel_psr_enable_locked() to intel_psr_compute_config() because we
need to be able to disable/enable PSR from atomic states without
connector and encoder state.

Reviewed-by: default avatarGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210922215242.66683-3-jose.souza@intel.com
parent 73262db6

drivers/gpu/drm/i915/display/intel_ddi.c

+0 −2
Original line number Diff line number Diff line
@@ -3034,7 +3034,6 @@ static void intel_enable_ddi_dp(struct intel_atomic_state *state, 
		intel_dp_stop_link_train(intel_dp, crtc_state);



	intel_edp_backlight_on(crtc_state, conn_state);

	intel_psr_enable(intel_dp, crtc_state, conn_state);



	if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)

		intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
@@ -3255,7 +3254,6 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, 


	intel_ddi_set_dp_msa(crtc_state, conn_state);



	intel_psr_update(intel_dp, crtc_state, conn_state);

	intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);

	intel_drrs_update(intel_dp, crtc_state);

drivers/gpu/drm/i915/display/intel_display.c

+9 −5
Original line number Diff line number Diff line
@@ -8098,11 +8098,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, 
		if (bp_gamma)

			PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);



		if (current_config->active_planes) {

			PIPE_CONF_CHECK_BOOL(has_psr);

			PIPE_CONF_CHECK_BOOL(has_psr2);

			PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);

			PIPE_CONF_CHECK_I(dc3co_exitline);

		}

	}



	PIPE_CONF_CHECK_BOOL(double_wide);
@@ -8158,7 +8160,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, 
		PIPE_CONF_CHECK_I(min_voltage_level);

	}



	if (fastset && (current_config->has_psr || pipe_config->has_psr))

	if (current_config->has_psr || pipe_config->has_psr)

		PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,

					    ~intel_hdmi_infoframe_enable(DP_SDP_VSC));

	else
@@ -10212,6 +10214,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) 
		intel_encoders_update_prepare(state);



	intel_dbuf_pre_plane_update(state);

	intel_psr_pre_plane_update(state);



	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {

		if (new_crtc_state->uapi.async_flip)
@@ -10275,6 +10278,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) 
	}



	intel_dbuf_post_plane_update(state);

	intel_psr_post_plane_update(state);



	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {

		intel_post_plane_update(state, crtc);

drivers/gpu/drm/i915/display/intel_display_types.h

+2 −1
Original line number Diff line number Diff line
@@ -1054,12 +1054,14 @@ struct intel_crtc_state { 
	struct intel_link_m_n dp_m2_n2;

	bool has_drrs;



	/* PSR is supported but might not be enabled due the lack of enabled planes */

	bool has_psr;

	bool has_psr2;

	bool enable_psr2_sel_fetch;

	bool req_psr2_sdp_prior_scanline;

	u32 dc3co_exitline;

	u16 su_y_granularity;

	struct drm_dp_vsc_sdp psr_vsc;



	/*

	 * Frequence the dpll for the port should run at. Differs from the
@@ -1523,7 +1525,6 @@ struct intel_psr { 
	u32 dc3co_exitline;

	u32 dc3co_exit_delay;

	struct delayed_work dc3co_work;

	struct drm_dp_vsc_sdp vsc;

};



struct intel_dp {

drivers/gpu/drm/i915/display/intel_dp.c

+3 −3
Original line number Diff line number Diff line
@@ -1674,7 +1674,7 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, 
{

	vsc->sdp_type = DP_SDP_VSC;



	if (intel_dp->psr.psr2_enabled) {

	if (crtc_state->has_psr2) {

		if (intel_dp->psr.colorimetry_support &&

		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {

			/* [PSR2, +Colorimetry] */
@@ -1828,7 +1828,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, 
		g4x_dp_set_clock(encoder, pipe_config);



	intel_vrr_compute_config(pipe_config, conn_state);

	intel_psr_compute_config(intel_dp, pipe_config);

	intel_psr_compute_config(intel_dp, pipe_config, conn_state);

	intel_drrs_compute_config(intel_dp, pipe_config, output_bpp,

				  constant_n);

	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
@@ -2888,7 +2888,7 @@ static void intel_write_dp_sdp(struct intel_encoder *encoder, 


void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,

			    const struct intel_crtc_state *crtc_state,

			    struct drm_dp_vsc_sdp *vsc)

			    const struct drm_dp_vsc_sdp *vsc)

{

	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

drivers/gpu/drm/i915/display/intel_dp.h

+1 −1
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, 
				  struct drm_dp_vsc_sdp *vsc);

void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,

			    const struct intel_crtc_state *crtc_state,

			    struct drm_dp_vsc_sdp *vsc);

			    const struct drm_dp_vsc_sdp *vsc);

void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,

			     const struct intel_crtc_state *crtc_state,

			     const struct drm_connector_state *conn_state);