Commit 73262db6 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/display: Match PSR2 selective fetch sequences with specification 



We were not completely following the selective fetch programming
sequence, here some things we were doing wrong:
- not programming plane selective fetch a PSR2_MAN_TRK_CTL registers
when doing a modeset
- programming PSR2_MAN_TRK_CTL out of vblank

With this changes the last remainig underrun found in Alderlake-P is
fixed.

Bspec: 55229
Tested-by: default avatarGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: default avatarGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210922215242.66683-2-jose.souza@intel.com
parent 27493cb8

drivers/gpu/drm/i915/display/intel_cursor.c

+3 −1
Original line number Diff line number Diff line
@@ -536,8 +536,10 @@ static void i9xx_update_cursor(struct intel_plane *plane, 
	if (DISPLAY_VER(dev_priv) >= 9)

		skl_write_cursor_wm(plane, crtc_state);



	if (!intel_crtc_needs_modeset(crtc_state))

	if (plane_state)

		intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0);

	else

		intel_psr2_disable_plane_sel_fetch(plane, crtc_state);



	if (plane->cursor.base != base ||

	    plane->cursor.size != fbc_ctl ||

drivers/gpu/drm/i915/display/intel_display.c

+5 −7
Original line number Diff line number Diff line
@@ -6819,11 +6819,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, 


	}



	if (!mode_changed) {

	ret = intel_psr2_sel_fetch_update(state, crtc);

	if (ret)

		return ret;

	}



	return 0;

}
@@ -9716,9 +9714,9 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state, 


		if (new_crtc_state->update_pipe)

			intel_pipe_fastset(old_crtc_state, new_crtc_state);

	}



	intel_psr2_program_trans_man_trk_ctl(new_crtc_state);

	}



	if (dev_priv->display.atomic_update_watermarks)

		dev_priv->display.atomic_update_watermarks(state, crtc);

drivers/gpu/drm/i915/display/intel_psr.c

+24 −9
Original line number Diff line number Diff line
@@ -561,15 +561,16 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 
		val |= EDP_PSR2_SU_SDP_SCANLINE;



	if (intel_dp->psr.psr2_sel_fetch_enabled) {

		u32 tmp;



		/* Wa_1408330847 */

		if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))

			intel_de_rmw(dev_priv, CHICKEN_PAR1_1,

				     DIS_RAM_BYPASS_PSR2_MAN_TRACK,

				     DIS_RAM_BYPASS_PSR2_MAN_TRACK);



		intel_de_write(dev_priv,

			       PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),

			       PSR2_MAN_TRK_CTL_ENABLE);

		tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));

		drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));

	} else if (HAS_PSR2_SEL_FETCH(dev_priv)) {

		intel_de_write(dev_priv,

			       PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0);
@@ -1450,6 +1451,18 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) 
	intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0);

}



void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,

					const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);

	enum pipe pipe = plane->pipe;



	if (!crtc_state->enable_psr2_sel_fetch)

		return;



	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);

}



void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,

					const struct intel_crtc_state *crtc_state,

					const struct intel_plane_state *plane_state,
@@ -1464,11 +1477,11 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 
	if (!crtc_state->enable_psr2_sel_fetch)

		return;



	val = plane_state ? plane_state->ctl : 0;

	val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE;

	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val);

	if (!val || plane->id == PLANE_CURSOR)

	if (plane->id == PLANE_CURSOR) {

		intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),

				  plane_state->ctl);

		return;

	}



	clip = &plane_state->psr2_sel_fetch_area;
@@ -1487,14 +1500,16 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 
	val = (drm_rect_height(clip) - 1) << 16;

	val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;

	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);



	intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),

			  PLANE_SEL_FETCH_CTL_ENABLE);

}



void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);



	if (!HAS_PSR2_SEL_FETCH(dev_priv) ||

	    !crtc_state->enable_psr2_sel_fetch)

	if (!crtc_state->enable_psr2_sel_fetch)

		return;



	intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),

drivers/gpu/drm/i915/display/intel_psr.h

+2 −0
Original line number Diff line number Diff line
@@ -51,6 +51,8 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, 
					const struct intel_crtc_state *crtc_state,

					const struct intel_plane_state *plane_state,

					int color_plane);

void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,

					const struct intel_crtc_state *crtc_state);

void intel_psr_pause(struct intel_dp *intel_dp);

void intel_psr_resume(struct intel_dp *intel_dp);

drivers/gpu/drm/i915/display/skl_universal_plane.c

+2 −2
Original line number Diff line number Diff line
@@ -656,6 +656,7 @@ skl_disable_plane(struct intel_plane *plane, 


	skl_write_plane_wm(plane, crtc_state);



	intel_psr2_disable_plane_sel_fetch(plane, crtc_state);

	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);

	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
@@ -1101,7 +1102,6 @@ skl_program_plane(struct intel_plane *plane, 
				  (plane_state->view.color_plane[1].y << 16) |

				   plane_state->view.color_plane[1].x);



	if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi))

	intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);



	/*