Commit 9b59ec8d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-5.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V fixes from Palmer Dabbelt:

 - A fix to avoid printing a warning when modules do not exercise any
   errata-dependent behavior and the SiFive errata are enabled.

 - A fix to the Microchip PFSOC to attach the L2 cache to the CPU nodes.

* tag 'riscv-for-linus-5.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: don't warn for sifive erratas in modules
  riscv: dts: microchip: hook up the mpfs' l2cache
parents a8ebfcd3 7fccd723

arch/riscv/boot/dts/microchip/mpfs.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ 
			riscv,isa = "rv64imafdc";

			clocks = <&clkcfg CLK_CPU>;

			tlb-split;

			next-level-cache = <&cctrllr>;

			status = "okay";



			cpu1_intc: interrupt-controller {
@@ -77,6 +78,7 @@ 
			riscv,isa = "rv64imafdc";

			clocks = <&clkcfg CLK_CPU>;

			tlb-split;

			next-level-cache = <&cctrllr>;

			status = "okay";



			cpu2_intc: interrupt-controller {
@@ -104,6 +106,7 @@ 
			riscv,isa = "rv64imafdc";

			clocks = <&clkcfg CLK_CPU>;

			tlb-split;

			next-level-cache = <&cctrllr>;

			status = "okay";



			cpu3_intc: interrupt-controller {
@@ -131,6 +134,7 @@ 
			riscv,isa = "rv64imafdc";

			clocks = <&clkcfg CLK_CPU>;

			tlb-split;

			next-level-cache = <&cctrllr>;

			status = "okay";

			cpu4_intc: interrupt-controller {

				#interrupt-cells = <1>;

arch/riscv/errata/sifive/errata.c

+2 −1
Original line number Diff line number Diff line
@@ -111,6 +111,7 @@ void __init_or_module sifive_errata_patch_func(struct alt_entry *begin, 
			cpu_apply_errata |= tmp;

		}

	}

	if (cpu_apply_errata != cpu_req_errata)

	if (stage != RISCV_ALTERNATIVES_MODULE &&

	    cpu_apply_errata != cpu_req_errata)

		warn_miss_errata(cpu_req_errata - cpu_apply_errata);

}