Unverified Commit 7fccd723 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge tag 'dt-fixes-for-palmer-5.19-rc6' of... 

Merge tag 'dt-fixes-for-palmer-5.19-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git into fixes

Microchip RISC-V devicetree fixes for 5.19-rc6

A single fix for mpfs.dtsi:
- The l2 cache controller was never hooked up in the dt, so userspace
  is presented with the wrong topology information, so it has been
  hooked up.

* tag 'dt-fixes-for-palmer-5.19-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git:
  riscv: dts: microchip: hook up the mpfs' l2cache
parents dc5cb7a8 efa310ba

arch/riscv/boot/dts/microchip/mpfs.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -50,6 +50,7 @@ 
			riscv,isa = "rv64imafdc";

			clocks = <&clkcfg CLK_CPU>;

			tlb-split;

			next-level-cache = <&cctrllr>;

			status = "okay";



			cpu1_intc: interrupt-controller {
@@ -77,6 +78,7 @@ 
			riscv,isa = "rv64imafdc";

			clocks = <&clkcfg CLK_CPU>;

			tlb-split;

			next-level-cache = <&cctrllr>;

			status = "okay";



			cpu2_intc: interrupt-controller {
@@ -104,6 +106,7 @@ 
			riscv,isa = "rv64imafdc";

			clocks = <&clkcfg CLK_CPU>;

			tlb-split;

			next-level-cache = <&cctrllr>;

			status = "okay";



			cpu3_intc: interrupt-controller {
@@ -131,6 +134,7 @@ 
			riscv,isa = "rv64imafdc";

			clocks = <&clkcfg CLK_CPU>;

			tlb-split;

			next-level-cache = <&cctrllr>;

			status = "okay";

			cpu4_intc: interrupt-controller {

				#interrupt-cells = <1>;