Unverified Commit 9b40194a authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!622 Intel: Add PMU support for Intel Emerald Rapids 

Merge Pull Request from: @yunyingsun 
 
Title: Add PMU support for Intel Emerald Rapids
 
Content:
This PR adds Performance Monitoring Unit(PMU) support for next Intel Xeon platform Emerald Rapids.

Totally 6 commits, including 4 EMR PMU enabling patches from v6.2 and 2 dependent patches from v5.14/v5.18:
(v6.2-rc6) 5a8a05f1 perf/x86/intel/cstate: Add Emerald Rapids
	(v5.18-rc4) 528c9f1d perf/x86/cstate: Add SAPPHIRERAPIDS_X CPU support
	(v5.14-rc1) 87bf399f perf/x86/cstate: Add ICELAKE_X and ICELAKE_D support
(v6.2-rc6) 6795e558 perf/x86/intel: Add Emerald Rapids
(v6.2-rc4) 5268a284 perf/x86/intel/uncore: Add Emerald Rapids
(v6.2-rc4) 69ced416 perf/x86/msr: Add Emerald Rapids

The four 6.2 patches above use a macro "INTEL_FAM6_EMERALDRAPIDS_X", which is introduced by:
(v6.1-rc1) 7beade0d x86/cpu: Add several Intel server CPU model numbers
This patch is already included in another PR:
https://gitee.com/openeuler/kernel/pulls/469

Note: this PR for PMU must be merged AFTER PR-469, otherwise there will be kernel compiling error complaining for missing definition of macro "INTEL_FAM6_EMERALDRAPIDS_X".

Intel-kernel issue:
https://gitee.com/openeuler/intel-kernel/issues/I6YO4Z
 
Test:
1. platform dependent core PMU event works with perf, like "L1-dcache-loads".
2. platform dependent uncore PMU event works with perf, like "uncore_imc_0/event=0x1/".
3. offcore event works with perf.
3. PEBS works with perf.
4. topdown works with perf.
With this PR(along with the patch from PR469) applied to kernel OLK-5.10, all tests above PASS on EMR.

Known issue:
N/A
 
Default config change:
N/A


 
 
Link:https://gitee.com/openeuler/kernel/pulls/622

 

Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Reviewed-by: default avatarAichun Shi <aichun.shi@intel.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 5216ad71 224a8e94

arch/x86/events/intel/core.c

+1 −0
Original line number Diff line number Diff line
@@ -5790,6 +5790,7 @@ __init int intel_pmu_init(void) 
		break;



	case INTEL_FAM6_SAPPHIRERAPIDS_X:

	case INTEL_FAM6_EMERALDRAPIDS_X:

		pmem = true;

		x86_pmu.late_ack = true;

		memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));

arch/x86/events/intel/cstate.c

+19 −6
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ 
 * Model specific counters:

 *	MSR_CORE_C1_RES: CORE C1 Residency Counter

 *			 perf code: 0x00

 *			 Available model: SLM,AMT,GLM,CNL,TNT

 *			 Available model: SLM,AMT,GLM,CNL,ICX,TNT

 *			 Scope: Core (each processor core has a MSR)

 *	MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter

 *			       perf code: 0x01
@@ -50,8 +50,8 @@ 
 *	MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter

 *			       perf code: 0x02

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL,

 *						TNT

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,

 *						TGL,TNT,SPR

 *			       Scope: Core

 *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter

 *			       perf code: 0x03
@@ -61,7 +61,7 @@ 
 *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.

 *			       perf code: 0x00

 *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL,

 *						KBL,CML,ICL,TGL,TNT

 *						KBL,CML,ICL,ICX,TGL,TNT,SPR

 *			       Scope: Package (physical package)

 *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.

 *			       perf code: 0x01
@@ -71,8 +71,8 @@ 
 *	MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.

 *			       perf code: 0x02

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL,

 *						TNT

 *						SKL,KNL,GLM,CNL,KBL,CML,ICL,ICX,

 *						TGL,TNT,SPR

 *			       Scope: Package (physical package)

 *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.

 *			       perf code: 0x03
@@ -563,6 +563,14 @@ static const struct cstate_model icl_cstates __initconst = { 
				  BIT(PERF_CSTATE_PKG_C10_RES),

};



static const struct cstate_model icx_cstates __initconst = {

	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |

				  BIT(PERF_CSTATE_CORE_C6_RES),



	.pkg_events		= BIT(PERF_CSTATE_PKG_C2_RES) |

				  BIT(PERF_CSTATE_PKG_C6_RES),

};



static const struct cstate_model slm_cstates __initconst = {

	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |

				  BIT(PERF_CSTATE_CORE_C6_RES),
@@ -647,6 +655,11 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 


	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,		&icl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE,		&icl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X,		&icx_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,		&icx_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&icx_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,	&icx_cstates),



	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,		&icl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		&icl_cstates),

	{ },

arch/x86/events/intel/uncore.c

+1 −0
Original line number Diff line number Diff line
@@ -1808,6 +1808,7 @@ static const struct x86_cpu_id intel_uncore_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,		&tgl_l_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		&tgl_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&spr_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,	&spr_uncore_init),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,	&snr_uncore_init),

	{},

};

arch/x86/events/msr.c

+1 −0
Original line number Diff line number Diff line
@@ -69,6 +69,7 @@ static bool test_intel(int idx, void *data) 
	case INTEL_FAM6_BROADWELL_G:

	case INTEL_FAM6_BROADWELL_X:

	case INTEL_FAM6_SAPPHIRERAPIDS_X:

	case INTEL_FAM6_EMERALDRAPIDS_X:



	case INTEL_FAM6_ATOM_SILVERMONT:

	case INTEL_FAM6_ATOM_SILVERMONT_D: