Commit 9a3a5a85 authored by Martin K. Petersen's avatar Martin K. Petersen
Browse files

Merge patch series "scsi: ufs: ufs-qcom: Debug clean ups" 

Andrew Halaney <ahalaney@redhat.com> says:

This patch series attempts to clean up some debug code paths in the
ufs-qcom driver.

Link: https://lore.kernel.org/r/20221201230810.1019834-1-ahalaney@redhat.com


Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parents c1635fbf 1026f7d3

drivers/ufs/host/ufs-qcom.c

+48 −87
Original line number Diff line number Diff line
@@ -22,9 +22,6 @@ 
#include <ufs/ufshci.h>

#include <ufs/ufs_quirks.h>



#define UFS_QCOM_DEFAULT_DBG_PRINT_EN	\

	(UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_TEST_BUS_EN)



enum {

	TSTBUS_UAWM,

	TSTBUS_UARM,
@@ -52,12 +49,6 @@ static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) 
	return container_of(rcd, struct ufs_qcom_host, rcdev);

}



static void ufs_qcom_dump_regs_wrapper(struct ufs_hba *hba, int offset, int len,

				       const char *prefix, void *priv)

{

	ufshcd_dump_regs(hba, offset, len * 4, prefix);

}



static int ufs_qcom_host_clk_get(struct device *dev,

		const char *name, struct clk **clk_out, bool optional)

{
@@ -689,12 +680,6 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 
	struct ufs_dev_params ufs_qcom_cap;

	int ret = 0;



	if (!dev_req_params) {

		pr_err("%s: incoming dev_req_params is NULL\n", __func__);

		ret = -EINVAL;

		goto out;

	}



	switch (status) {

	case PRE_CHANGE:

		ufshcd_init_pwr_dev_param(&ufs_qcom_cap);
@@ -718,7 +703,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba, 
					       dev_max_params,

					       dev_req_params);

		if (ret) {

			pr_err("%s: failed to determine capabilities\n",

			dev_err(hba->dev, "%s: failed to determine capabilities\n",

					__func__);

			goto out;

		}
@@ -1046,7 +1031,6 @@ static int ufs_qcom_init(struct ufs_hba *hba) 
	if (hba->dev->id < MAX_UFS_QCOM_HOSTS)

		ufs_qcom_hosts[hba->dev->id] = host;



	host->dbg_print_en |= UFS_QCOM_DEFAULT_DBG_PRINT_EN;

	ufs_qcom_get_default_testbus_cfg(host);

	err = ufs_qcom_testbus_config(host);

	if (err) {
@@ -1195,77 +1179,11 @@ static int ufs_qcom_clk_scale_notify(struct ufs_hba *hba, 
	return err;

}



static void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba,

		void *priv, void (*print_fn)(struct ufs_hba *hba,

		int offset, int num_regs, const char *str, void *priv))

{

	u32 reg;

	struct ufs_qcom_host *host;



	if (unlikely(!hba)) {

		pr_err("%s: hba is NULL\n", __func__);

		return;

	}

	if (unlikely(!print_fn)) {

		dev_err(hba->dev, "%s: print_fn is NULL\n", __func__);

		return;

	}



	host = ufshcd_get_variant(hba);

	if (!(host->dbg_print_en & UFS_QCOM_DBG_PRINT_REGS_EN))

		return;



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);

	print_fn(hba, reg, 44, "UFS_UFS_DBG_RD_REG_OCSC ", priv);



	reg = ufshcd_readl(hba, REG_UFS_CFG1);

	reg |= UTP_DBG_RAMS_EN;

	ufshcd_writel(hba, reg, REG_UFS_CFG1);



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);

	print_fn(hba, reg, 32, "UFS_UFS_DBG_RD_EDTL_RAM ", priv);



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);

	print_fn(hba, reg, 128, "UFS_UFS_DBG_RD_DESC_RAM ", priv);



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);

	print_fn(hba, reg, 64, "UFS_UFS_DBG_RD_PRDT_RAM ", priv);



	/* clear bit 17 - UTP_DBG_RAMS_EN */

	ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);

	print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UAWM ", priv);



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);

	print_fn(hba, reg, 4, "UFS_DBG_RD_REG_UARM ", priv);



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);

	print_fn(hba, reg, 48, "UFS_DBG_RD_REG_TXUC ", priv);



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);

	print_fn(hba, reg, 27, "UFS_DBG_RD_REG_RXUC ", priv);



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);

	print_fn(hba, reg, 19, "UFS_DBG_RD_REG_DFC ", priv);



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);

	print_fn(hba, reg, 34, "UFS_DBG_RD_REG_TRLUT ", priv);



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);

	print_fn(hba, reg, 9, "UFS_DBG_RD_REG_TMRLUT ", priv);

}



static void ufs_qcom_enable_test_bus(struct ufs_qcom_host *host)

{

	if (host->dbg_print_en & UFS_QCOM_DBG_PRINT_TEST_BUS_EN) {

	ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN,

			UFS_REG_TEST_BUS_EN, REG_UFS_CFG1);

	ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1);

	} else {

		ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, 0, REG_UFS_CFG1);

		ufshcd_rmwl(host->hba, TEST_BUS_EN, 0, REG_UFS_CFG1);

	}

}



static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host)
@@ -1374,10 +1292,53 @@ int ufs_qcom_testbus_config(struct ufs_qcom_host *host) 


static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba)

{

	u32 reg;

	struct ufs_qcom_host *host;



	host = ufshcd_get_variant(hba);



	ufshcd_dump_regs(hba, REG_UFS_SYS1CLK_1US, 16 * 4,

			 "HCI Vendor Specific Registers ");



	ufs_qcom_print_hw_debug_reg_all(hba, NULL, ufs_qcom_dump_regs_wrapper);

	reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_REG_OCSC);

	ufshcd_dump_regs(hba, reg, 44 * 4, "UFS_UFS_DBG_RD_REG_OCSC ");



	reg = ufshcd_readl(hba, REG_UFS_CFG1);

	reg |= UTP_DBG_RAMS_EN;

	ufshcd_writel(hba, reg, REG_UFS_CFG1);



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_EDTL_RAM);

	ufshcd_dump_regs(hba, reg, 32 * 4, "UFS_UFS_DBG_RD_EDTL_RAM ");



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_DESC_RAM);

	ufshcd_dump_regs(hba, reg, 128 * 4, "UFS_UFS_DBG_RD_DESC_RAM ");



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_UFS_DBG_RD_PRDT_RAM);

	ufshcd_dump_regs(hba, reg, 64 * 4, "UFS_UFS_DBG_RD_PRDT_RAM ");



	/* clear bit 17 - UTP_DBG_RAMS_EN */

	ufshcd_rmwl(hba, UTP_DBG_RAMS_EN, 0, REG_UFS_CFG1);



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UAWM);

	ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UAWM ");



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_UARM);

	ufshcd_dump_regs(hba, reg, 4 * 4, "UFS_DBG_RD_REG_UARM ");



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TXUC);

	ufshcd_dump_regs(hba, reg, 48 * 4, "UFS_DBG_RD_REG_TXUC ");



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_RXUC);

	ufshcd_dump_regs(hba, reg, 27 * 4, "UFS_DBG_RD_REG_RXUC ");



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_DFC);

	ufshcd_dump_regs(hba, reg, 19 * 4, "UFS_DBG_RD_REG_DFC ");



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TRLUT);

	ufshcd_dump_regs(hba, reg, 34 * 4, "UFS_DBG_RD_REG_TRLUT ");



	reg = ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT);

	ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT ");

}



/**

drivers/ufs/host/ufs-qcom.h

+0 −11
Original line number Diff line number Diff line
@@ -113,15 +113,6 @@ enum { 
	MASK_CLK_NS_REG                     = 0xFFFC00,

};



/* QCOM UFS debug print bit mask */

#define UFS_QCOM_DBG_PRINT_REGS_EN	BIT(0)

#define UFS_QCOM_DBG_PRINT_ICE_REGS_EN	BIT(1)

#define UFS_QCOM_DBG_PRINT_TEST_BUS_EN	BIT(2)



#define UFS_QCOM_DBG_PRINT_ALL	\

	(UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_ICE_REGS_EN | \

	 UFS_QCOM_DBG_PRINT_TEST_BUS_EN)



/* QUniPro Vendor specific attributes */

#define PA_VS_CONFIG_REG1	0x9000

#define DME_VS_CORE_CLK_CTRL	0xD002
@@ -212,8 +203,6 @@ struct ufs_qcom_host { 


	u32 dev_ref_clk_en_mask;



	/* Bitmask for enabling debug prints */

	u32 dbg_print_en;

	struct ufs_qcom_testbus testbus;



	/* Reset control of HCI */