Commit 985a74d8 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/audio: Unify register bit naming 



Rename a few g4x bits to match the ibx+ bits.

Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Cc: Takashi Iwai <tiwai@suse.de>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarKai Vehmanen <kai.vehmanen@linux.intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221026170150.2654-7-ville.syrjala@linux.intel.com
parent 011aa42e

drivers/gpu/drm/i915/display/intel_audio.c

+5 −5
Original line number Diff line number Diff line
@@ -340,7 +340,7 @@ static void g4x_audio_codec_disable(struct intel_encoder *encoder, 


	/* Invalidate ELD */

	tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);

	tmp &= ~G4X_ELDV;

	tmp &= ~G4X_ELD_VALID;

	intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);

}
@@ -355,13 +355,13 @@ static void g4x_audio_codec_enable(struct intel_encoder *encoder, 
	int len, i;



	if (intel_eld_uptodate(connector,

			       G4X_AUD_CNTL_ST, G4X_ELDV,

			       G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,

			       G4X_AUD_CNTL_ST, G4X_ELD_VALID,

			       G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK,

			       G4X_HDMIW_HDMIEDID))

		return;



	tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);

	tmp &= ~(G4X_ELDV | G4X_ELD_ADDR_MASK);

	tmp &= ~(G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK);

	len = REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);

	intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);
@@ -371,7 +371,7 @@ static void g4x_audio_codec_enable(struct intel_encoder *encoder, 
			       *((const u32 *)eld + i));



	tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);

	tmp |= G4X_ELDV;

	tmp |= G4X_ELD_VALID;

	intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);

}

drivers/gpu/drm/i915/display/intel_audio_regs.h

+2 −2
Original line number Diff line number Diff line
@@ -9,9 +9,9 @@ 
#include "i915_reg_defs.h"



#define G4X_AUD_CNTL_ST			_MMIO(0x620B4)

#define   G4X_ELDV			REG_BIT(14)

#define   G4X_ELD_VALID			REG_BIT(14)

#define   G4X_ELD_BUFFER_SIZE_MASK	REG_GENMASK(13, 9)

#define   G4X_ELD_ADDR_MASK		REG_GENMASK(8, 5)

#define   G4X_ELD_ADDRESS_MASK		REG_GENMASK(8, 5)

#define   G4X_ELD_ACK			REG_BIT(4)

#define G4X_HDMIW_HDMIEDID		_MMIO(0x6210C)