Commit 011aa42e authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/audio: Use REG_BIT() & co. 



Switch the audio registers to REG_BIT() & co.

Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Cc: Takashi Iwai <tiwai@suse.de>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarKai Vehmanen <kai.vehmanen@linux.intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221026170150.2654-6-ville.syrjala@linux.intel.com
parent 669d7fd6

drivers/gpu/drm/i915/display/intel_audio.c

+6 −9
Original line number Diff line number Diff line
@@ -362,7 +362,7 @@ static void g4x_audio_codec_enable(struct intel_encoder *encoder, 


	tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);

	tmp &= ~(G4X_ELDV | G4X_ELD_ADDR_MASK);

	len = (tmp >> 9) & 0x1f;		/* ELD buffer size */

	len = REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);

	intel_de_write(i915, G4X_AUD_CNTL_ST, tmp);



	len = min(drm_eld_size(eld) / 4, len);
@@ -700,7 +700,7 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder, 
	enum pipe pipe = crtc->pipe;

	enum port port = encoder->port;

	struct ilk_audio_regs regs;

	u32 tmp, eldv;

	u32 tmp;



	if (drm_WARN_ON(&i915->drm, port == PORT_A))

		return;
@@ -717,11 +717,9 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder, 
		tmp |= AUD_CONFIG_N_VALUE_INDEX;

	intel_de_write(i915, regs.aud_config, tmp);



	eldv = IBX_ELD_VALID(port);



	/* Invalidate ELD */

	tmp = intel_de_read(i915, regs.aud_cntrl_st2);

	tmp &= ~eldv;

	tmp &= ~IBX_ELD_VALID(port);

	intel_de_write(i915, regs.aud_cntrl_st2, tmp);

}
@@ -736,8 +734,8 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder, 
	enum port port = encoder->port;

	const u8 *eld = connector->eld;

	struct ilk_audio_regs regs;

	u32 tmp, eldv;

	int len, i;

	u32 tmp;



	if (drm_WARN_ON(&i915->drm, port == PORT_A))

		return;
@@ -751,11 +749,10 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder, 


	ilk_audio_regs_init(i915, pipe, &regs);



	eldv = IBX_ELD_VALID(port);



	/* Invalidate ELD */

	tmp = intel_de_read(i915, regs.aud_cntrl_st2);

	tmp &= ~eldv;

	tmp &= ~IBX_ELD_VALID(port);

	intel_de_write(i915, regs.aud_cntrl_st2, tmp);



	/* Reset ELD write address */
@@ -771,7 +768,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder, 


	/* ELD valid */

	tmp = intel_de_read(i915, regs.aud_cntrl_st2);

	tmp |= eldv;

	tmp |= IBX_ELD_VALID(port);

	intel_de_write(i915, regs.aud_cntrl_st2, tmp);



	/* Enable timestamps */

drivers/gpu/drm/i915/display/intel_audio_regs.h

+39 −42
Original line number Diff line number Diff line
@@ -9,9 +9,10 @@ 
#include "i915_reg_defs.h"



#define G4X_AUD_CNTL_ST			_MMIO(0x620B4)

#define   G4X_ELDV			(1 << 14)

#define   G4X_ELD_ADDR_MASK		(0xf << 5)

#define   G4X_ELD_ACK			(1 << 4)

#define   G4X_ELDV			REG_BIT(14)

#define   G4X_ELD_BUFFER_SIZE_MASK	REG_GENMASK(13, 9)

#define   G4X_ELD_ADDR_MASK		REG_GENMASK(8, 5)

#define   G4X_ELD_ACK			REG_BIT(4)

#define G4X_HDMIW_HDMIEDID		_MMIO(0x6210C)



#define _IBX_HDMIW_HDMIEDID_A		0xE2050
@@ -22,12 +23,12 @@ 
#define _IBX_AUD_CNTL_ST_B		0xE21B4

#define IBX_AUD_CNTL_ST(pipe)		_MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \

						  _IBX_AUD_CNTL_ST_B)

#define   IBX_ELD_BUFFER_SIZE_MASK	(0x1f << 10)

#define   IBX_ELD_ADDRESS_MASK		(0x1f << 5)

#define   IBX_ELD_ACK			(1 << 4)

#define   IBX_ELD_BUFFER_SIZE_MASK	REG_GENMASK(14, 10)

#define   IBX_ELD_ADDRESS_MASK		REG_GENMASK(9, 5)

#define   IBX_ELD_ACK			REG_BIT(4)

#define IBX_AUD_CNTL_ST2		_MMIO(0xE20C0)

#define   IBX_CP_READY(port)		((1 << 1) << (((port) - 1) * 4))

#define   IBX_ELD_VALID(port)		((1 << 0) << (((port) - 1) * 4))

#define   IBX_CP_READY(port)		REG_BIT(((port) - 1) * 4 + 1)

#define   IBX_ELD_VALID(port)		REG_BIT(((port) - 1) * 4 + 0)



#define _CPT_HDMIW_HDMIEDID_A		0xE5050

#define _CPT_HDMIW_HDMIEDID_B		0xE5150
@@ -54,34 +55,30 @@ 
#define _VLV_AUD_CONFIG_A		(VLV_DISPLAY_BASE + 0x62000)

#define _VLV_AUD_CONFIG_B		(VLV_DISPLAY_BASE + 0x62100)

#define VLV_AUD_CFG(pipe)		_MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)



#define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)

#define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)

#define   AUD_CONFIG_UPPER_N_SHIFT		20

#define   AUD_CONFIG_UPPER_N_MASK		(0xff << 20)

#define   AUD_CONFIG_LOWER_N_SHIFT		4

#define   AUD_CONFIG_LOWER_N_MASK		(0xfff << 4)

#define   AUD_CONFIG_N_MASK			(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK)

#define   AUD_CONFIG_N(n) \

	(((((n) >> 12) & 0xff) << AUD_CONFIG_UPPER_N_SHIFT) |	\

	 (((n) & 0xfff) << AUD_CONFIG_LOWER_N_SHIFT))

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT	16

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK	(0xf << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175	(0 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200	(1 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000	(2 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027	(3 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000	(4 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054	(5 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176	(6 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250	(7 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	(8 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	(9 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_296703	(10 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_297000	(11 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_593407	(12 << 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_594000	(13 << 16)

#define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)

#define   AUD_CONFIG_N_VALUE_INDEX		REG_BIT(29)

#define   AUD_CONFIG_N_PROG_ENABLE		REG_BIT(28)

#define   AUD_CONFIG_UPPER_N_MASK		REG_GENMASK(27, 20)

#define   AUD_CONFIG_LOWER_N_MASK		REG_GENMASK(15, 4)

#define   AUD_CONFIG_N_MASK			(AUD_CONFIG_UPPER_N_MASK | \

						 AUD_CONFIG_LOWER_N_MASK)

#define   AUD_CONFIG_N(n)			(REG_FIELD_PREP(AUD_CONFIG_UPPER_N_MASK, (n) >> 12) | \

						 REG_FIELD_PREP(AUD_CONFIG_LOWER_N_MASK, (n) & 0xfff))

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK	REG_GENMASK(19, 16)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25175	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 0)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_25200	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 1)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27000	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 2)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_27027	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 3)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54000	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 4)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_54054	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 5)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74176	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 6)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_74250	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 7)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148352	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 8)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_148500	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 9)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_296703	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 10)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_297000	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 11)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_593407	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 12)

#define   AUD_CONFIG_PIXEL_CLOCK_HDMI_594000	REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 13)

#define   AUD_CONFIG_DISABLE_NCTS		REG_BIT(3)



#define _HSW_AUD_CONFIG_A		0x65000

#define _HSW_AUD_CONFIG_B		0x65100
@@ -94,9 +91,9 @@ 
#define _HSW_AUD_M_CTS_ENABLE_A		0x65028

#define _HSW_AUD_M_CTS_ENABLE_B		0x65128

#define HSW_AUD_M_CTS_ENABLE(trans)	_MMIO_TRANS(trans, _HSW_AUD_M_CTS_ENABLE_A, _HSW_AUD_M_CTS_ENABLE_B)

#define   AUD_M_CTS_M_VALUE_INDEX	(1 << 21)

#define   AUD_M_CTS_M_PROG_ENABLE	(1 << 20)

#define   AUD_CONFIG_M_MASK		0xfffff

#define   AUD_M_CTS_M_VALUE_INDEX	REG_BIT(21)

#define   AUD_M_CTS_M_PROG_ENABLE	REG_BIT(20)

#define   AUD_CONFIG_M_MASK		REG_GENMASK(19, 0)



#define _HSW_AUD_DIP_ELD_CTRL_ST_A	0x650b4

#define _HSW_AUD_DIP_ELD_CTRL_ST_B	0x651b4
@@ -125,7 +122,7 @@ 
#define  AUD_ENABLE_SDP_SPLIT		REG_BIT(31)



#define HSW_AUD_CHICKENBIT		_MMIO(0x65f10)

#define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)

#define   SKL_AUD_CODEC_WAKE_SIGNAL	REG_BIT(15)



#define AUD_FREQ_CNTRL			_MMIO(0x65900)

#define AUD_PIN_BUF_CTL			_MMIO(0x48414)