Commit 955ad0c8 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.18-2022-03-09' of... 

Merge tag 'amd-drm-next-5.18-2022-03-09' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-next

amd-drm-next-5.18-2022-03-09:

amdgpu:
- Misc code cleanups
- Misc display fixes
- PSR display fixes
- More RAS cleanup
- Hotplug fix
- Bump minor version for hotplug tests
- SR-IOV fixes
- GC 10.3.7 updates
- Remove some firmwares which are no longer used
- Mode2 reset refactor
- Aldebaran fixes
- Add VCN fwlog feature for VCN debugging
- CS code cleanup
- Fix clang warning
- Fix CS clean up rebase breakage

amdkfd:
- SVM fixes
- SMI event fixes and cleanups
- vmid_pasid mapping fix for gfx10.3

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220309224439.2178877-1-alexander.deucher@amd.com
parents 482d7b58 96a2f0f2

drivers/gpu/drm/amd/amdgpu/aldebaran.c

+50 −16
Original line number Diff line number Diff line
@@ -31,6 +31,17 @@ 
#include "amdgpu_psp.h"

#include "amdgpu_xgmi.h"



static bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;



	if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&

	     adev->gmc.xgmi.connected_to_cpu))

		return true;



	return false;

}



static struct amdgpu_reset_handler *

aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl,

			    struct amdgpu_reset_context *reset_context)
@@ -48,7 +59,7 @@ aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl, 
		}

	}



	if (adev->gmc.xgmi.connected_to_cpu) {

	if (aldebaran_is_mode2_default(reset_ctl)) {

		list_for_each_entry(handler, &reset_ctl->reset_handlers,

				     handler_list) {

			if (handler->reset_method == AMD_RESET_METHOD_MODE2) {
@@ -136,18 +147,31 @@ static int 
aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,

			      struct amdgpu_reset_context *reset_context)

{

	struct amdgpu_device *tmp_adev = NULL;

	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;

	struct amdgpu_device *tmp_adev = NULL;

	struct list_head reset_device_list;

	int r = 0;



	dev_dbg(adev->dev, "aldebaran perform hw reset\n");

	if (reset_context->hive == NULL) {

	if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) &&

	    reset_context->hive == NULL) {

		/* Wrong context, return error */

		return -EINVAL;

	}



	list_for_each_entry(tmp_adev, &reset_context->hive->device_list,

			     gmc.xgmi.head) {

	INIT_LIST_HEAD(&reset_device_list);

	if (reset_context->hive) {

		list_for_each_entry (tmp_adev,

				     &reset_context->hive->device_list,

				     gmc.xgmi.head)

			list_add_tail(&tmp_adev->reset_list,

				      &reset_device_list);

	} else {

		list_add_tail(&reset_context->reset_req_dev->reset_list,

			      &reset_device_list);

	}



	list_for_each_entry (tmp_adev, &reset_device_list, reset_list) {

		mutex_lock(&tmp_adev->reset_cntl->reset_lock);

		tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2;

	}
@@ -155,8 +179,7 @@ aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, 
	 * Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch

	 * them together so that they can be completed asynchronously on multiple nodes

	 */

	list_for_each_entry(tmp_adev, &reset_context->hive->device_list,

			     gmc.xgmi.head) {

	list_for_each_entry (tmp_adev, &reset_device_list, reset_list) {

		/* For XGMI run all resets in parallel to speed up the process */

		if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {

			if (!queue_work(system_unbound_wq,
@@ -174,9 +197,7 @@ aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, 


	/* For XGMI wait for all resets to complete before proceed */

	if (!r) {

		list_for_each_entry(tmp_adev,

				     &reset_context->hive->device_list,

				     gmc.xgmi.head) {

		list_for_each_entry (tmp_adev, &reset_device_list, reset_list) {

			if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {

				flush_work(&tmp_adev->reset_cntl->reset_work);

				r = tmp_adev->asic_reset_res;
@@ -186,8 +207,7 @@ aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl, 
		}

	}



	list_for_each_entry(tmp_adev, &reset_context->hive->device_list,

			     gmc.xgmi.head) {

	list_for_each_entry (tmp_adev, &reset_device_list, reset_list) {

		mutex_unlock(&tmp_adev->reset_cntl->reset_lock);

		tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE;

	}
@@ -319,16 +339,30 @@ static int 
aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,

				  struct amdgpu_reset_context *reset_context)

{

	int r;

	struct amdgpu_device *tmp_adev = NULL;

	struct list_head reset_device_list;

	int r;



	if (reset_context->hive == NULL) {

	if (reset_context->reset_req_dev->ip_versions[MP1_HWIP][0] ==

		    IP_VERSION(13, 0, 2) &&

	    reset_context->hive == NULL) {

		/* Wrong context, return error */

		return -EINVAL;

	}



	list_for_each_entry(tmp_adev, &reset_context->hive->device_list,

			     gmc.xgmi.head) {

	INIT_LIST_HEAD(&reset_device_list);

	if (reset_context->hive) {

		list_for_each_entry (tmp_adev,

				     &reset_context->hive->device_list,

				     gmc.xgmi.head)

			list_add_tail(&tmp_adev->reset_list,

				      &reset_device_list);

	} else {

		list_add_tail(&reset_context->reset_req_dev->reset_list,

			      &reset_device_list);

	}



	list_for_each_entry (tmp_adev, &reset_device_list, reset_list) {

		dev_info(tmp_adev->dev,

			 "GPU reset succeeded, trying to resume\n");

		r = aldebaran_mode2_restore_ip(tmp_adev);

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+3 −95
Original line number Diff line number Diff line
@@ -60,7 +60,6 @@ 
#include <drm/amdgpu_drm.h>

#include <drm/drm_gem.h>

#include <drm/drm_ioctl.h>

#include <drm/gpu_scheduler.h>



#include <kgd_kfd_interface.h>

#include "dm_pp_interface.h"
@@ -233,6 +232,9 @@ extern int amdgpu_cik_support; 
#endif

extern int amdgpu_num_kcq;



#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)

extern int amdgpu_vcnfw_log;



#define AMDGPU_VM_MAX_NUM_CTX			4096

#define AMDGPU_SG_THRESHOLD			(256*1024*1024)

#define AMDGPU_DEFAULT_GTT_SIZE_MB		3072ULL /* 3GB by default */
@@ -274,9 +276,6 @@ extern int amdgpu_num_kcq; 
#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)



struct amdgpu_device;

struct amdgpu_ib;

struct amdgpu_cs_parser;

struct amdgpu_job;

struct amdgpu_irq_src;

struct amdgpu_fpriv;

struct amdgpu_bo_va_mapping;
@@ -464,20 +463,6 @@ struct amdgpu_flip_work { 
};





/*

 * CP & rings.

 */



struct amdgpu_ib {

	struct amdgpu_sa_bo		*sa_bo;

	uint32_t			length_dw;

	uint64_t			gpu_addr;

	uint32_t			*ptr;

	uint32_t			flags;

};



extern const struct drm_sched_backend_ops amdgpu_sched_ops;



/*

 * file private structure

 */
@@ -493,79 +478,6 @@ struct amdgpu_fpriv { 


int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);



int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

		  unsigned size,

		  enum amdgpu_ib_pool_type pool,

		  struct amdgpu_ib *ib);

void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,

		    struct dma_fence *f);

int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,

		       struct amdgpu_ib *ibs, struct amdgpu_job *job,

		       struct dma_fence **f);

int amdgpu_ib_pool_init(struct amdgpu_device *adev);

void amdgpu_ib_pool_fini(struct amdgpu_device *adev);

int amdgpu_ib_ring_tests(struct amdgpu_device *adev);



/*

 * CS.

 */

struct amdgpu_cs_chunk {

	uint32_t		chunk_id;

	uint32_t		length_dw;

	void			*kdata;

};



struct amdgpu_cs_post_dep {

	struct drm_syncobj *syncobj;

	struct dma_fence_chain *chain;

	u64 point;

};



struct amdgpu_cs_parser {

	struct amdgpu_device	*adev;

	struct drm_file		*filp;

	struct amdgpu_ctx	*ctx;



	/* chunks */

	unsigned		nchunks;

	struct amdgpu_cs_chunk	*chunks;



	/* scheduler job object */

	struct amdgpu_job	*job;

	struct drm_sched_entity	*entity;



	/* buffer objects */

	struct ww_acquire_ctx		ticket;

	struct amdgpu_bo_list		*bo_list;

	struct amdgpu_mn		*mn;

	struct amdgpu_bo_list_entry	vm_pd;

	struct list_head		validated;

	struct dma_fence		*fence;

	uint64_t			bytes_moved_threshold;

	uint64_t			bytes_moved_vis_threshold;

	uint64_t			bytes_moved;

	uint64_t			bytes_moved_vis;



	/* user fence */

	struct amdgpu_bo_list_entry	uf_entry;



	unsigned			num_post_deps;

	struct amdgpu_cs_post_dep	*post_deps;

};



static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,

				      uint32_t ib_idx, int idx)

{

	return p->job->ibs[ib_idx].ptr[idx];

}



static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,

				       uint32_t ib_idx, int idx,

				       uint32_t value)

{

	p->job->ibs[ib_idx].ptr[idx] = value;

}



/*

 * Writeback

 */
@@ -1436,10 +1348,6 @@ static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { retu 
static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }

#endif



int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,

			   uint64_t addr, struct amdgpu_bo **bo,

			   struct amdgpu_bo_va_mapping **mapping);



#if defined(CONFIG_DRM_AMD_DC)

int amdgpu_dm_display_resume(struct amdgpu_device *adev );

#else

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

+15 −1
Original line number Diff line number Diff line
@@ -26,6 +26,8 @@ 
#include "gc/gc_10_3_0_sh_mask.h"

#include "oss/osssys_5_0_0_offset.h"

#include "oss/osssys_5_0_0_sh_mask.h"

#include "athub/athub_2_1_0_offset.h"

#include "athub/athub_2_1_0_sh_mask.h"

#include "soc15_common.h"

#include "v10_structs.h"

#include "nv.h"
@@ -606,6 +608,18 @@ static int wave_control_execute_v10_3(struct amdgpu_device *adev, 
	return 0;

}



static bool get_atc_vmid_pasid_mapping_info_v10_3(struct amdgpu_device *adev,

					uint8_t vmid, uint16_t *p_pasid)

{

	uint32_t value;



	value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)

		     + vmid);

	*p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;



	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);

}



static void set_vm_context_page_table_base_v10_3(struct amdgpu_device *adev,

		uint32_t vmid, uint64_t page_table_base)

{
@@ -788,7 +802,7 @@ const struct kfd2kgd_calls gfx_v10_3_kfd2kgd = { 
	.hqd_destroy = hqd_destroy_v10_3,

	.hqd_sdma_destroy = hqd_sdma_destroy_v10_3,

	.wave_control_execute = wave_control_execute_v10_3,

	.get_atc_vmid_pasid_mapping_info = NULL,

	.get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info_v10_3,

	.set_vm_context_page_table_base = set_vm_context_page_table_base_v10_3,

	.program_trap_handler_settings = program_trap_handler_settings_v10_3,

#if 0

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+3 −2
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 


#include <drm/amdgpu_drm.h>

#include <drm/drm_syncobj.h>

#include "amdgpu_cs.h"

#include "amdgpu.h"

#include "amdgpu_trace.h"

#include "amdgpu_gmc.h"
@@ -782,12 +783,12 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) 
				memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);

				amdgpu_bo_kunmap(aobj);



				r = amdgpu_ring_parse_cs(ring, p, j);

				r = amdgpu_ring_parse_cs(ring, p, p->job, ib);

				if (r)

					return r;

			} else {

				ib->ptr = (uint32_t *)kptr;

				r = amdgpu_ring_patch_cs_in_place(ring, p, j);

				r = amdgpu_ring_patch_cs_in_place(ring, p, p->job, ib);

				amdgpu_bo_kunmap(aobj);

				if (r)

					return r;

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.h

0 → 100644
+80 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2022 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef __AMDGPU_CS_H__

#define __AMDGPU_CS_H__



#include "amdgpu_job.h"

#include "amdgpu_bo_list.h"

#include "amdgpu_ring.h"



struct amdgpu_bo_va_mapping;



struct amdgpu_cs_chunk {

	uint32_t		chunk_id;

	uint32_t		length_dw;

	void			*kdata;

};



struct amdgpu_cs_post_dep {

	struct drm_syncobj *syncobj;

	struct dma_fence_chain *chain;

	u64 point;

};



struct amdgpu_cs_parser {

	struct amdgpu_device	*adev;

	struct drm_file		*filp;

	struct amdgpu_ctx	*ctx;



	/* chunks */

	unsigned		nchunks;

	struct amdgpu_cs_chunk	*chunks;



	/* scheduler job object */

	struct amdgpu_job	*job;

	struct drm_sched_entity	*entity;



	/* buffer objects */

	struct ww_acquire_ctx		ticket;

	struct amdgpu_bo_list		*bo_list;

	struct amdgpu_mn		*mn;

	struct amdgpu_bo_list_entry	vm_pd;

	struct list_head		validated;

	struct dma_fence		*fence;

	uint64_t			bytes_moved_threshold;

	uint64_t			bytes_moved_vis_threshold;

	uint64_t			bytes_moved;

	uint64_t			bytes_moved_vis;



	/* user fence */

	struct amdgpu_bo_list_entry	uf_entry;



	unsigned			num_post_deps;

	struct amdgpu_cs_post_dep	*post_deps;

};



int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,

			   uint64_t addr, struct amdgpu_bo **bo,

			   struct amdgpu_bo_va_mapping **mapping);



#endif