Commit 94ff371e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2021-10-15' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



UAPI Changes:

- No Functional change, but a clarification around I915_TILING values (Matt).

Driver Changes:

- Changes around async flip VT-d w/a (Ville)
- Delete bogus NULL check in intel_ddi_encoder_destroy (Dan)
- DP link training improvements and DP per-lane driver settings (Ville)
- Free the returned object of acpi_evaluate_dsm (Zenghui)
- Fixes and improvements around DP's UHBR and MST (Jani)
- refactor plane config + pin out (Dave)
- remove unused include in intel_dsi_vbt.c (Lucas)
- some code clean up (Lucas, Jani)
- gracefully disable dual eDP (Jani)
- Remove memory frequency calculation (Jose)
- Fix oops on platforms w/o hpd support (Ville)
- Clean up PXP Kconfig info (Rodrigo)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YWnMORrixyw90O3/@intel.com
parents 1176d15f c974cf01

drivers/gpu/drm/i915/Kconfig

+5 −5
Original line number Diff line number Diff line
@@ -132,15 +132,15 @@ config DRM_I915_GVT_KVMGT 
	  Intel GVT-g.



config DRM_I915_PXP

	bool "Enable Intel PXP support for Intel Gen12 and newer platform"

	bool "Enable Intel PXP support"

	depends on DRM_I915

	depends on INTEL_MEI && INTEL_MEI_PXP

	default n

	help

	  PXP (Protected Xe Path) is an i915 component, available on GEN12 and

	  newer GPUs, that helps to establish the hardware protected session and

	  manage the status of the alive software session, as well as its life

	  cycle.

	  PXP (Protected Xe Path) is an i915 component, available on graphics

	  version 12 and newer GPUs, that helps to establish the hardware

	  protected session and manage the status of the alive software session,

	  as well as its life cycle.



menu "drm/i915 Debugging"

depends on DRM_I915

drivers/gpu/drm/i915/Makefile

+5 −1
Original line number Diff line number Diff line
@@ -47,13 +47,15 @@ i915-y += i915_drv.o \ 
	  intel_dram.o \

	  intel_memory_region.o \

	  intel_pch.o \

	  intel_pcode.o \

	  intel_pm.o \

	  intel_region_ttm.o \

	  intel_runtime_pm.o \

	  intel_sideband.o \

	  intel_sbi.o \

	  intel_step.o \

	  intel_uncore.o \

	  intel_wakeref.o \

	  vlv_sideband.o \

	  vlv_suspend.o



# core library code
@@ -214,6 +216,7 @@ i915-y += \ 
	display/intel_drrs.o \

	display/intel_dsb.o \

	display/intel_fb.o \

	display/intel_fb_pin.o \

	display/intel_fbc.o \

	display/intel_fdi.o \

	display/intel_fifo_underrun.o \
@@ -223,6 +226,7 @@ i915-y += \ 
	display/intel_hotplug.o \

	display/intel_lpe_audio.o \

	display/intel_overlay.o \

	display/intel_plane_initial.o \

	display/intel_psr.o \

	display/intel_quirks.o \

	display/intel_sprite.o \

drivers/gpu/drm/i915/display/g4x_dp.c

+2 −2
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ 
#include "intel_hdmi.h"

#include "intel_hotplug.h"

#include "intel_pps.h"

#include "intel_sideband.h"

#include "vlv_sideband.h"



struct dp_link_dpll {

	int clock;
@@ -637,7 +637,7 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp, 
	/* enable with pattern 1 (as per spec) */



	intel_dp_program_link_training_pattern(intel_dp, crtc_state,

					       DP_TRAINING_PATTERN_1);

					       DP_PHY_DPRX, DP_TRAINING_PATTERN_1);



	/*

	 * Magic for VLV/CHV. We _must_ first set up the register

drivers/gpu/drm/i915/display/g4x_hdmi.c

+1 −1
Original line number Diff line number Diff line
@@ -14,8 +14,8 @@ 
#include "intel_fifo_underrun.h"

#include "intel_hdmi.h"

#include "intel_hotplug.h"

#include "intel_sideband.h"

#include "intel_sdvo.h"

#include "vlv_sideband.h"



static void intel_hdmi_prepare(struct intel_encoder *encoder,

			       const struct intel_crtc_state *crtc_state)

drivers/gpu/drm/i915/display/icl_dsi.c

+7 −7
Original line number Diff line number Diff line
@@ -233,7 +233,7 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 
		 * Program voltage swing and pre-emphasis level values as per

		 * table in BSPEC under DDI buffer programing

		 */

		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));

		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));

		tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);

		tmp |= SCALING_MODE_SEL(0x2);

		tmp |= TAP2_DISABLE | TAP3_DISABLE;
@@ -247,7 +247,7 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 
		tmp |= RTERM_SELECT(0x6);

		intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp);



		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));

		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));

		tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |

			 RCOMP_SCALAR_MASK);

		tmp |= SWING_SEL_UPPER(0x2);
@@ -455,7 +455,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 
		tmp &= ~FRC_LATENCY_OPTIM_MASK;

		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);

		intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp);

		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));

		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));

		tmp &= ~FRC_LATENCY_OPTIM_MASK;

		tmp |= FRC_LATENCY_OPTIM_VAL(0x5);

		intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
@@ -470,7 +470,7 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 
				       tmp);



			tmp = intel_de_read(dev_priv,

					    ICL_PORT_PCS_DW1_LN0(phy));

					    ICL_PORT_PCS_DW1_LN(0, phy));

			tmp &= ~LATENCY_OPTIM_MASK;

			tmp |= LATENCY_OPTIM_VAL(0x1);

			intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
@@ -489,7 +489,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 


	/* clear common keeper enable bit */

	for_each_dsi_phy(phy, intel_dsi->phys) {

		tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));

		tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));

		tmp &= ~COMMON_KEEPER_EN;

		intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);

		tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy));
@@ -510,7 +510,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 


	/* Clear training enable to change swing values */

	for_each_dsi_phy(phy, intel_dsi->phys) {

		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));

		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));

		tmp &= ~TX_TRAINING_EN;

		intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);

		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));
@@ -523,7 +523,7 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 


	/* Set training enable to trigger update */

	for_each_dsi_phy(phy, intel_dsi->phys) {

		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));

		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));

		tmp |= TX_TRAINING_EN;

		intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);

		tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy));