Commit 9265a4f0 authored by Alex Elder's avatar Alex Elder Committed by Jakub Kicinski
Browse files

net: ipa: define even more IPA register fields 



Define the fields for the FLAVOR_0, IDLE_INDICATION_CFG,
QTIME_TIMESTAMP_CFG, TIMERS_XO_CLK_DIV_CFG and TIMERS_PULSE_GRAN_CFG
IPA registers for all supported IPA versions.

Create enumerated types to identify fields for these IPA registers.
Use IPA_REG_FIELDS() to specify the field mask values defined for
these registers, for each supported version of IPA.

Use ipa_reg_bit() and ipa_reg_encode() to build up the values to be
written to these registers.  Use ipa_reg_decode() to extract field
values from the FLAVOR_0 register.

Remove the definition of the no-longer-used *_FMASK symbols.

Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent b5c35fa4

drivers/net/ipa/ipa_endpoint.c

+3 −3
Original line number Diff line number Diff line
@@ -1854,8 +1854,8 @@ int ipa_endpoint_config(struct ipa *ipa) 
	val = ioread32(ipa->reg_virt + ipa_reg_offset(reg));



	/* Our RX is an IPA producer */

	rx_base = u32_get_bits(val, IPA_PROD_LOWEST_FMASK);

	max = rx_base + u32_get_bits(val, IPA_MAX_PROD_PIPES_FMASK);

	rx_base = ipa_reg_decode(reg, PROD_LOWEST, val);

	max = rx_base + ipa_reg_decode(reg, MAX_PROD_PIPES, val);

	if (max > IPA_ENDPOINT_MAX) {

		dev_err(dev, "too many endpoints (%u > %u)\n",

			max, IPA_ENDPOINT_MAX);
@@ -1864,7 +1864,7 @@ int ipa_endpoint_config(struct ipa *ipa) 
	rx_mask = GENMASK(max - 1, rx_base);



	/* Our TX is an IPA consumer */

	max = u32_get_bits(val, IPA_MAX_CONS_PIPES_FMASK);

	max = ipa_reg_decode(reg, MAX_CONS_PIPES, val);

	tx_mask = GENMASK(max - 1, 0);



	ipa->available = rx_mask | tx_mask;

drivers/net/ipa/ipa_main.c

+12 −12
Original line number Diff line number Diff line
@@ -361,31 +361,31 @@ static void ipa_qtime_config(struct ipa *ipa) 


	reg = ipa_reg(ipa, QTIME_TIMESTAMP_CFG);

	/* Set DPL time stamp resolution to use Qtime (instead of 1 msec) */

	val = u32_encode_bits(DPL_TIMESTAMP_SHIFT, DPL_TIMESTAMP_LSB_FMASK);

	val |= u32_encode_bits(1, DPL_TIMESTAMP_SEL_FMASK);

	val = ipa_reg_encode(reg, DPL_TIMESTAMP_LSB, DPL_TIMESTAMP_SHIFT);

	val |= ipa_reg_bit(reg, DPL_TIMESTAMP_SEL);

	/* Configure tag and NAT Qtime timestamp resolution as well */

	val |= u32_encode_bits(TAG_TIMESTAMP_SHIFT, TAG_TIMESTAMP_LSB_FMASK);

	val |= u32_encode_bits(NAT_TIMESTAMP_SHIFT, NAT_TIMESTAMP_LSB_FMASK);

	val = ipa_reg_encode(reg, TAG_TIMESTAMP_LSB, TAG_TIMESTAMP_SHIFT);

	val = ipa_reg_encode(reg, NAT_TIMESTAMP_LSB, NAT_TIMESTAMP_SHIFT);



	iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));



	/* Set granularity of pulse generators used for other timers */

	reg = ipa_reg(ipa, TIMERS_PULSE_GRAN_CFG);

	val = u32_encode_bits(IPA_GRAN_100_US, GRAN_0_FMASK);

	val |= u32_encode_bits(IPA_GRAN_1_MS, GRAN_1_FMASK);

	val |= u32_encode_bits(IPA_GRAN_1_MS, GRAN_2_FMASK);

	val = ipa_reg_encode(reg, PULSE_GRAN_0, IPA_GRAN_100_US);

	val |= ipa_reg_encode(reg, PULSE_GRAN_1, IPA_GRAN_1_MS);

	val |= ipa_reg_encode(reg, PULSE_GRAN_2, IPA_GRAN_1_MS);



	iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));



	/* Actual divider is 1 more than value supplied here */

	reg = ipa_reg(ipa, TIMERS_XO_CLK_DIV_CFG);

	offset = ipa_reg_offset(reg);

	val = u32_encode_bits(IPA_XO_CLOCK_DIVIDER - 1, DIV_VALUE_FMASK);

	val = ipa_reg_encode(reg, DIV_VALUE, IPA_XO_CLOCK_DIVIDER - 1);



	iowrite32(val, ipa->reg_virt + offset);



	/* Divider value is set; re-enable the common timer clock divider */

	val |= u32_encode_bits(1, DIV_ENABLE_FMASK);

	val |= ipa_reg_bit(reg, DIV_ENABLE);



	iowrite32(val, ipa->reg_virt + offset);

}
@@ -435,10 +435,10 @@ static void ipa_idle_indication_cfg(struct ipa *ipa, 
	u32 val;



	reg = ipa_reg(ipa, IDLE_INDICATION_CFG);

	val = u32_encode_bits(enter_idle_debounce_thresh,

			      ENTER_IDLE_DEBOUNCE_THRESH_FMASK);

	val = ipa_reg_encode(reg, ENTER_IDLE_DEBOUNCE_THRESH,

			     enter_idle_debounce_thresh);

	if (const_non_idle_enable)

		val |= CONST_NON_IDLE_ENABLE_FMASK;

		val |= ipa_reg_bit(reg, CONST_NON_IDLE_ENABLE);



	iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));

}

drivers/net/ipa/ipa_reg.h

+27 −16
Original line number Diff line number Diff line
@@ -316,30 +316,41 @@ enum ipa_reg_ipa_tx_cfg_field_id { 
};



/* FLAVOR_0 register */

#define IPA_MAX_PIPES_FMASK			GENMASK(3, 0)

#define IPA_MAX_CONS_PIPES_FMASK		GENMASK(12, 8)

#define IPA_MAX_PROD_PIPES_FMASK		GENMASK(20, 16)

#define IPA_PROD_LOWEST_FMASK			GENMASK(27, 24)

enum ipa_reg_flavor_0_field_id {

	MAX_PIPES,

	MAX_CONS_PIPES,

	MAX_PROD_PIPES,

	PROD_LOWEST,

};



/* IDLE_INDICATION_CFG register */

#define ENTER_IDLE_DEBOUNCE_THRESH_FMASK	GENMASK(15, 0)

#define CONST_NON_IDLE_ENABLE_FMASK		GENMASK(16, 16)

enum ipa_reg_idle_indication_cfg_field_id {

	ENTER_IDLE_DEBOUNCE_THRESH,

	CONST_NON_IDLE_ENABLE,

};



/* QTIME_TIMESTAMP_CFG register */

#define DPL_TIMESTAMP_LSB_FMASK			GENMASK(4, 0)

#define DPL_TIMESTAMP_SEL_FMASK			GENMASK(7, 7)

#define TAG_TIMESTAMP_LSB_FMASK			GENMASK(12, 8)

#define NAT_TIMESTAMP_LSB_FMASK			GENMASK(20, 16)

enum ipa_reg_qtime_timestamp_cfg_field_id {

	DPL_TIMESTAMP_LSB,

	DPL_TIMESTAMP_SEL,

	TAG_TIMESTAMP_LSB,

	NAT_TIMESTAMP_LSB,

};



/* TIMERS_XO_CLK_DIV_CFG register */

#define DIV_VALUE_FMASK				GENMASK(8, 0)

#define DIV_ENABLE_FMASK			GENMASK(31, 31)

enum ipa_reg_timers_xo_clk_div_cfg_field_id {

	DIV_VALUE,

	DIV_ENABLE,

};



/* TIMERS_PULSE_GRAN_CFG register */

#define GRAN_0_FMASK				GENMASK(2, 0)

#define GRAN_1_FMASK				GENMASK(5, 3)

#define GRAN_2_FMASK				GENMASK(8, 6)

/* Values for GRAN_x fields of TIMERS_PULSE_GRAN_CFG */

enum ipa_reg_timers_pulse_gran_cfg_field_id {

	PULSE_GRAN_0,

	PULSE_GRAN_1,

	PULSE_GRAN_2,

};



/* Values for IPA_GRAN_x fields of TIMERS_PULSE_GRAN_CFG */

enum ipa_pulse_gran {

	IPA_GRAN_10_US				= 0x0,

	IPA_GRAN_20_US				= 0x1,

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

+19 −2
Original line number Diff line number Diff line
@@ -140,9 +140,26 @@ static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { 


IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);



IPA_REG(FLAVOR_0, flavor_0, 0x00000210);

static const u32 ipa_reg_flavor_0_fmask[] = {

	[MAX_PIPES]					= GENMASK(3, 0),

						/* Bits 4-7 reserved */

	[MAX_CONS_PIPES]				= GENMASK(12, 8),

						/* Bits 13-15 reserved */

	[MAX_PROD_PIPES]				= GENMASK(20, 16),

						/* Bits 21-23 reserved */

	[PROD_LOWEST]					= GENMASK(27, 24),

						/* Bits 28-31 reserved */

};



IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);



static const u32 ipa_reg_idle_indication_cfg_fmask[] = {

	[ENTER_IDLE_DEBOUNCE_THRESH]			= GENMASK(15, 0),

	[CONST_NON_IDLE_ENABLE]				= BIT(16),

						/* Bits 17-31 reserved */

};



IPA_REG(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220);

IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000220);



IPA_REG_STRIDE(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,

	       0x00000400, 0x0020);

drivers/net/ipa/reg/ipa_reg-v4.11.c

+45 −5
Original line number Diff line number Diff line
@@ -168,15 +168,55 @@ static const u32 ipa_reg_ipa_tx_cfg_fmask[] = { 


IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);



IPA_REG(FLAVOR_0, flavor_0, 0x00000210);

static const u32 ipa_reg_flavor_0_fmask[] = {

	[MAX_PIPES]					= GENMASK(4, 0),

						/* Bits 5-7 reserved */

	[MAX_CONS_PIPES]				= GENMASK(12, 8),

						/* Bits 13-15 reserved */

	[MAX_PROD_PIPES]				= GENMASK(20, 16),

						/* Bits 21-23 reserved */

	[PROD_LOWEST]					= GENMASK(27, 24),

						/* Bits 28-31 reserved */

};



IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);



IPA_REG(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);

static const u32 ipa_reg_idle_indication_cfg_fmask[] = {

	[ENTER_IDLE_DEBOUNCE_THRESH]			= GENMASK(15, 0),

	[CONST_NON_IDLE_ENABLE]				= BIT(16),

						/* Bits 17-31 reserved */

};



IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);



IPA_REG(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);

static const u32 ipa_reg_qtime_timestamp_cfg_fmask[] = {

	[DPL_TIMESTAMP_LSB]				= GENMASK(4, 0),

						/* Bits 5-6 reserved */

	[DPL_TIMESTAMP_SEL]				= BIT(7),

	[TAG_TIMESTAMP_LSB]				= GENMASK(12, 8),

						/* Bits 13-15 reserved */

	[NAT_TIMESTAMP_LSB]				= GENMASK(20, 16),

						/* Bits 21-31 reserved */

};



IPA_REG(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);

IPA_REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);



static const u32 ipa_reg_timers_xo_clk_div_cfg_fmask[] = {

	[DIV_VALUE]					= GENMASK(8, 0),

						/* Bits 9-30 reserved */

	[DIV_ENABLE]					= BIT(31),

};



IPA_REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);



static const u32 ipa_reg_timers_pulse_gran_cfg_fmask[] = {

	[PULSE_GRAN_0]					= GENMASK(2, 0),

	[PULSE_GRAN_1]					= GENMASK(5, 3),

	[PULSE_GRAN_2]					= GENMASK(8, 6),

						/* Bits 9-31 reserved */

};



IPA_REG(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);

IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);



IPA_REG_STRIDE(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,

	       0x00000400, 0x0020);