Commit b5c35fa4 authored by Alex Elder's avatar Alex Elder Committed by Jakub Kicinski
Browse files

net: ipa: define more IPA register fields 



Define the fields for the LOCAL_PKT_PROC_CNTXT, COUNTER_CFG, and
IPA_TX_CFG IPA registers for all supported IPA versions.

Create enumerated types to identify fields for these IPA registers.
Use IPA_REG_FIELDS() to specify the field mask values defined for
these registers, for each supported version of IPA.

Use ipa_reg_bit() and ipa_reg_encode() to build up the values to be
written to these registers.  Remove the definition of the *_FMASK
symbols as well as proc_cntxt_base_addr_encoded(), because they are
no longer needed.

Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 62b9c009

drivers/net/ipa/ipa_main.c

+3 −4
Original line number Diff line number Diff line
@@ -214,7 +214,7 @@ static void ipa_hardware_config_tx(struct ipa *ipa) 


	val = ioread32(ipa->reg_virt + offset);



	val &= ~PA_MASK_EN_FMASK;

	val &= ~ipa_reg_bit(reg, PA_MASK_EN);



	iowrite32(val, ipa->reg_virt + offset);

}
@@ -398,7 +398,8 @@ static void ipa_hardware_config_counter(struct ipa *ipa) 
	u32 val;



	reg = ipa_reg(ipa, COUNTER_CFG);

	val = u32_encode_bits(granularity, AGGR_GRANULARITY_FMASK);

	/* If defined, EOT_COAL_GRANULARITY is 0 */

	val = ipa_reg_encode(reg, AGGR_GRANULARITY, granularity);

	iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));

}
@@ -690,8 +691,6 @@ static void ipa_validate_build(void) 


	/* Aggregation granularity value can't be 0, and must fit */

	BUILD_BUG_ON(!ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY));

	BUILD_BUG_ON(ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY) >

			field_max(AGGR_GRANULARITY_FMASK));

}



/**

drivers/net/ipa/ipa_mem.c

+1 −1
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ int ipa_mem_setup(struct ipa *ipa) 
	offset = ipa->mem_offset + mem->offset;



	reg = ipa_reg(ipa, LOCAL_PKT_PROC_CNTXT);

	val = proc_cntxt_base_addr_encoded(ipa->version, offset);

	val = ipa_reg_encode(reg, IPA_BASE_ADDR, offset);

	iowrite32(val, ipa->reg_virt + ipa_reg_offset(reg));



	return 0;

drivers/net/ipa/ipa_reg.h

+21 −29
Original line number Diff line number Diff line
@@ -289,39 +289,31 @@ enum ipa_bcr_compat { 
};



/* LOCAL_PKT_PROC_CNTXT register */

/* Encoded value for LOCAL_PKT_PROC_CNTXT register BASE_ADDR field */

static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version,

					       u32 addr)

{

	if (version < IPA_VERSION_4_5)

		return u32_encode_bits(addr, GENMASK(16, 0));



	return u32_encode_bits(addr, GENMASK(17, 0));

}

enum ipa_reg_local_pkt_proc_cntxt_field_id {

	IPA_BASE_ADDR,

};



/* COUNTER_CFG register */

/* The next field is not present for IPA v3.5+ */

#define EOT_COAL_GRANULARITY_FMASK		GENMASK(3, 0)

#define AGGR_GRANULARITY_FMASK			GENMASK(8, 4)

enum ipa_reg_counter_cfg_field_id {

	EOT_COAL_GRANULARITY,				/* Not v3.5+ */

	AGGR_GRANULARITY,

};



/* IPA_TX_CFG register */

/* The next three fields are not present for IPA v4.0+ */

#define TX0_PREFETCH_DISABLE_FMASK		GENMASK(0, 0)

#define TX1_PREFETCH_DISABLE_FMASK		GENMASK(1, 1)

#define PREFETCH_ALMOST_EMPTY_SIZE_FMASK	GENMASK(4, 2)

/* The next six fields are present for IPA v4.0+ */

#define PREFETCH_ALMOST_EMPTY_SIZE_TX0_FMASK	GENMASK(5, 2)

#define DMAW_SCND_OUTSD_PRED_THRESHOLD_FMASK	GENMASK(9, 6)

#define DMAW_SCND_OUTSD_PRED_EN_FMASK		GENMASK(10, 10)

#define DMAW_MAX_BEATS_256_DIS_FMASK		GENMASK(11, 11)

#define PA_MASK_EN_FMASK			GENMASK(12, 12)

#define PREFETCH_ALMOST_EMPTY_SIZE_TX1_FMASK	GENMASK(16, 13)

/* The next field is present for IPA v4.5+ */

#define DUAL_TX_ENABLE_FMASK			GENMASK(17, 17)

/* The next field is present for IPA v4.2+, but not IPA v4.5 */

#define SSPND_PA_NO_START_STATE_FMASK		GENMASK(18, 18)

/* The next field is present for IPA v4.2 only */

#define SSPND_PA_NO_BQ_STATE_FMASK		GENMASK(19, 19)

enum ipa_reg_ipa_tx_cfg_field_id {

	TX0_PREFETCH_DISABLE,				/* Not v4.0+ */

	TX1_PREFETCH_DISABLE,				/* Not v4.0+ */

	PREFETCH_ALMOST_EMPTY_SIZE,			/* Not v4.0+ */

	PREFETCH_ALMOST_EMPTY_SIZE_TX0,			/* v4.0+ */

	DMAW_SCND_OUTSD_PRED_THRESHOLD,			/* v4.0+ */

	DMAW_SCND_OUTSD_PRED_EN,			/* v4.0+ */

	DMAW_MAX_BEATS_256_DIS,				/* v4.0+ */

	PA_MASK_EN,					/* v4.0+ */

	PREFETCH_ALMOST_EMPTY_SIZE_TX1,			/* v4.0+ */

	DUAL_TX_ENABLE,					/* v4.5+ */

	SSPND_PA_NO_START_STATE,			/* v4,2+, not v4.5 */

	SSPND_PA_NO_BQ_STATE,				/* v4.2 only */

};



/* FLAVOR_0 register */

#define IPA_MAX_PIPES_FMASK			GENMASK(3, 0)

drivers/net/ipa/reg/ipa_reg-v3.1.c

+13 −2
Original line number Diff line number Diff line
@@ -107,13 +107,24 @@ IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c); 


IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0);



static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {

	[IPA_BASE_ADDR]					= GENMASK(16, 0),

						/* Bits 17-31 reserved */

};



/* Offset must be a multiple of 8 */

IPA_REG(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);

IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);



/* Valid bits defined by ipa->available */

IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);



IPA_REG(COUNTER_CFG, counter_cfg, 0x000001f0);

static const u32 ipa_reg_counter_cfg_fmask[] = {

	[EOT_COAL_GRANULARITY]				= GENMASK(3, 0),

	[AGGR_GRANULARITY]				= GENMASK(8, 4),

						/* Bits 5-31 reserved */

};



IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);



IPA_REG_STRIDE(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type,

	       0x00000400, 0x0020);

drivers/net/ipa/reg/ipa_reg-v3.5.1.c

+21 −3
Original line number Diff line number Diff line
@@ -112,15 +112,33 @@ IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c); 


IPA_REG(IPA_BCR, ipa_bcr, 0x000001d0);



static const u32 ipa_reg_local_pkt_proc_cntxt_fmask[] = {

	[IPA_BASE_ADDR]					= GENMASK(16, 0),

						/* Bits 17-31 reserved */

};



/* Offset must be a multiple of 8 */

IPA_REG(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);

IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);



/* Valid bits defined by ipa->available */

IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);



IPA_REG(COUNTER_CFG, counter_cfg, 0x000001f0);

static const u32 ipa_reg_counter_cfg_fmask[] = {

						/* Bits 0-3 reserved */

	[AGGR_GRANULARITY]				= GENMASK(8, 4),

						/* Bits 5-31 reserved */

};



IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);



static const u32 ipa_reg_ipa_tx_cfg_fmask[] = {

	[TX0_PREFETCH_DISABLE]				= BIT(0),

	[TX1_PREFETCH_DISABLE]				= BIT(1),

	[PREFETCH_ALMOST_EMPTY_SIZE]			= GENMASK(4, 2),

						/* Bits 5-31 reserved */

};



IPA_REG(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);

IPA_REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);



IPA_REG(FLAVOR_0, flavor_0, 0x00000210);