Commit 924ad0e8 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Give C0DRB3/C1DRB3 a _BW suffix 



These are the 965g/g45/g33 specific DRB registers. Give them
a suitable suffix so we can add their counterparts for other
platforms.

Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210421153401.13847-4-ville.syrjala@linux.intel.com
parent f765a5b4

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

+2 −2
Original line number Diff line number Diff line
@@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) 
		 * banks of memory are paired and unswizzled on the

		 * uneven portion, so leave that as unknown.

		 */

		if (intel_uncore_read16(uncore, C0DRB3) ==

		    intel_uncore_read16(uncore, C1DRB3)) {

		if (intel_uncore_read16(uncore, C0DRB3_BW) ==

		    intel_uncore_read16(uncore, C1DRB3_BW)) {

			swizzle_x = I915_BIT_6_SWIZZLE_9_10;

			swizzle_y = I915_BIT_6_SWIZZLE_9;

		}

drivers/gpu/drm/i915/i915_debugfs.c

+2 −2
Original line number Diff line number Diff line
@@ -622,9 +622,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data) 
		seq_printf(m, "DDC2 = 0x%08x\n",

			   intel_uncore_read(uncore, DCC2));

		seq_printf(m, "C0DRB3 = 0x%04x\n",

			   intel_uncore_read16(uncore, C0DRB3));

			   intel_uncore_read16(uncore, C0DRB3_BW));

		seq_printf(m, "C1DRB3 = 0x%04x\n",

			   intel_uncore_read16(uncore, C1DRB3));

			   intel_uncore_read16(uncore, C1DRB3_BW));

	} else if (INTEL_GEN(dev_priv) >= 6) {

		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",

			   intel_uncore_read(uncore, MAD_DIMM_C0));

drivers/gpu/drm/i915/i915_reg.h

+2 −2
Original line number Diff line number Diff line
@@ -3787,8 +3787,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define CSHRDDR3CTL_DDR3       (1 << 2)



/* 965 MCH register controlling DRAM channel configuration */

#define C0DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x206)

#define C1DRB3			_MMIO(MCHBAR_MIRROR_BASE + 0x606)

#define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)

#define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)



/* snb MCH registers for reading the DRAM channel configuration */

#define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)