Commit f765a5b4 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Read C0DRB3/C1DRB3 as 16 bits again 



We've defined C0DRB3/C1DRB3 as 16 bit registers, so access them
as such.

Fixes: 1c8242c3 ("drm/i915: Use unchecked writes for setting up the fences")
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210421153401.13847-3-ville.syrjala@linux.intel.com
parent ed52c62d

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

+2 −2
Original line number Diff line number Diff line
@@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) 
		 * banks of memory are paired and unswizzled on the

		 * uneven portion, so leave that as unknown.

		 */

		if (intel_uncore_read(uncore, C0DRB3) ==

		    intel_uncore_read(uncore, C1DRB3)) {

		if (intel_uncore_read16(uncore, C0DRB3) ==

		    intel_uncore_read16(uncore, C1DRB3)) {

			swizzle_x = I915_BIT_6_SWIZZLE_9_10;

			swizzle_y = I915_BIT_6_SWIZZLE_9;

		}