Intel: perf/x86: Add constraint to create guest LBR event without hw counter

mainline inclusion
from mainline-v5.9-rc1
commit 097e4311
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I47H3V


CVE: NA

--------------------------------

commit 097e4311 upstream
Backport summary: backport to kernel 4.19.57 for ICX perf topdown support

The hypervisor may request the perf subsystem to schedule a time window
to directly access the LBR records msrs for its own use. Normally, it would
create a guest LBR event with callstack mode enabled, which is scheduled
along with other ordinary LBR events on the host but in an exclusive way.

To avoid wasting a counter for the guest LBR event, the perf tracks its
hw->idx via INTEL_PMC_IDX_FIXED_VLBR and assigns it with a fake VLBR
counter with the help of new vlbr_constraint. As with the BTS event,
there is actually no hardware counter assigned for the guest LBR event.

Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200514083054.62538-5-like.xu@linux.intel.com


Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Jackie Liu <liuyun01@kylinos.cn>
Signed-off-by: Zheng Zengkai <zhengzengkai@huawei.com>
Reviewed-by: Wei Li <liwei391@huawei.com>
Reviewed-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>