Commit 8f40bade authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
Browse files

arm64/sysreg: Standardise naming for ID_AA64MMFR2_EL1.VARange 



The kernel refers to ID_AA64MMFR2_EL1.VARange as LVA. In preparation for
automatic generation of defines for the system registers bring the naming
used by the kernel in sync with that of DDI0487H.a. No functional change.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarKristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-12-broonie@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 6fcd0193

arch/arm64/include/asm/assembler.h

+1 −1
Original line number Diff line number Diff line
@@ -612,7 +612,7 @@ alternative_endif 
	.macro	offset_ttbr1, ttbr, tmp

#ifdef CONFIG_ARM64_VA_BITS_52

	mrs_s	\tmp, SYS_ID_AA64MMFR2_EL1

	and	\tmp, \tmp, #(0xf << ID_AA64MMFR2_EL1_LVA_SHIFT)

	and	\tmp, \tmp, #(0xf << ID_AA64MMFR2_EL1_VARange_SHIFT)

	cbnz	\tmp, .Lskipoffs_\@

	orr	\ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET

.Lskipoffs_\@ :

arch/arm64/include/asm/sysreg.h

+1 −1
Original line number Diff line number Diff line
@@ -815,7 +815,7 @@ 
#define ID_AA64MMFR2_EL1_ST_SHIFT	28

#define ID_AA64MMFR2_EL1_NV_SHIFT	24

#define ID_AA64MMFR2_EL1_CCIDX_SHIFT	20

#define ID_AA64MMFR2_EL1_LVA_SHIFT	16

#define ID_AA64MMFR2_EL1_VARange_SHIFT	16

#define ID_AA64MMFR2_EL1_IESB_SHIFT	12

#define ID_AA64MMFR2_EL1_LSM_SHIFT	8

#define ID_AA64MMFR2_EL1_UAO_SHIFT	4

arch/arm64/kernel/cpufeature.c

+1 −1
Original line number Diff line number Diff line
@@ -388,7 +388,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 
	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LVA_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0),

arch/arm64/kernel/head.S

+2 −2
Original line number Diff line number Diff line
@@ -99,7 +99,7 @@ SYM_CODE_START(primary_entry) 
	 */

#if VA_BITS > 48

	mrs_s	x0, SYS_ID_AA64MMFR2_EL1

	tst	x0, #0xf << ID_AA64MMFR2_EL1_LVA_SHIFT

	tst	x0, #0xf << ID_AA64MMFR2_EL1_VARange_SHIFT

	mov	x0, #VA_BITS

	mov	x25, #VA_BITS_MIN

	csel	x25, x25, x0, eq
@@ -677,7 +677,7 @@ SYM_FUNC_START(__cpu_secondary_check52bitva) 
	b.ne	2f



	mrs_s	x0, SYS_ID_AA64MMFR2_EL1

	and	x0, x0, #(0xf << ID_AA64MMFR2_EL1_LVA_SHIFT)

	and	x0, x0, #(0xf << ID_AA64MMFR2_EL1_VARange_SHIFT)

	cbnz	x0, 2f



	update_early_cpu_boot_status \