Commit 6fcd0193 authored by Kristina Martsenko's avatar Kristina Martsenko Committed by Catalin Marinas
Browse files

arm64/sysreg: Standardise naming for ID_AA64MMFR1_EL1 fields 



In preparation for converting the ID_AA64MMFR1_EL1 system register
defines to automatic generation, rename them to follow the conventions
used by other automatically generated registers:

 * Add _EL1 in the register name.

 * Rename fields to match the names in the ARM ARM:
   * LOR -> LO
   * HPD -> HPDS
   * VHE -> VH
   * HADBS -> HAFDBS
   * SPECSEI -> SpecSEI
   * VMIDBITS -> VMIDBits

There should be no functional change as a result of this patch.

Signed-off-by: default avatarKristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarKristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-11-broonie@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 07d7d848

arch/arm64/include/asm/cpufeature.h

+4 −4
Original line number Diff line number Diff line
@@ -868,14 +868,14 @@ static inline bool cpu_has_hw_af(void) 


	mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);

	return cpuid_feature_extract_unsigned_field(mmfr1,

						ID_AA64MMFR1_HADBS_SHIFT);

						ID_AA64MMFR1_EL1_HAFDBS_SHIFT);

}



static inline bool cpu_has_pan(void)

{

	u64 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);

	return cpuid_feature_extract_unsigned_field(mmfr1,

						    ID_AA64MMFR1_PAN_SHIFT);

						    ID_AA64MMFR1_EL1_PAN_SHIFT);

}



#ifdef CONFIG_ARM64_AMU_EXTN
@@ -896,8 +896,8 @@ static inline unsigned int get_vmid_bits(u64 mmfr1) 
	int vmid_bits;



	vmid_bits = cpuid_feature_extract_unsigned_field(mmfr1,

						ID_AA64MMFR1_VMIDBITS_SHIFT);

	if (vmid_bits == ID_AA64MMFR1_VMIDBITS_16)

						ID_AA64MMFR1_EL1_VMIDBits_SHIFT);

	if (vmid_bits == ID_AA64MMFR1_EL1_VMIDBits_16)

		return 16;



	/*

arch/arm64/include/asm/el2_setup.h

+1 −1
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ 
/* LORegions */

.macro __init_el2_lor

	mrs	x1, id_aa64mmfr1_el1

	ubfx	x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4

	ubfx	x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4

	cbz	x0, .Lskip_lor_\@

	msr_s	SYS_LORC_EL1, xzr

.Lskip_lor_\@:

arch/arm64/include/asm/sysreg.h

+20 −20
Original line number Diff line number Diff line
@@ -783,26 +783,26 @@ 
#endif



/* id_aa64mmfr1 */

#define ID_AA64MMFR1_ECBHB_SHIFT	60

#define ID_AA64MMFR1_TIDCP1_SHIFT	52

#define ID_AA64MMFR1_HCX_SHIFT		40

#define ID_AA64MMFR1_AFP_SHIFT		44

#define ID_AA64MMFR1_ETS_SHIFT		36

#define ID_AA64MMFR1_TWED_SHIFT		32

#define ID_AA64MMFR1_XNX_SHIFT		28

#define ID_AA64MMFR1_SPECSEI_SHIFT	24

#define ID_AA64MMFR1_PAN_SHIFT		20

#define ID_AA64MMFR1_LOR_SHIFT		16

#define ID_AA64MMFR1_HPD_SHIFT		12

#define ID_AA64MMFR1_VHE_SHIFT		8

#define ID_AA64MMFR1_VMIDBITS_SHIFT	4

#define ID_AA64MMFR1_HADBS_SHIFT	0



#define ID_AA64MMFR1_VMIDBITS_8		0

#define ID_AA64MMFR1_VMIDBITS_16	2



#define ID_AA64MMFR1_TIDCP1_NI		0

#define ID_AA64MMFR1_TIDCP1_IMP		1

#define ID_AA64MMFR1_EL1_ECBHB_SHIFT		60

#define ID_AA64MMFR1_EL1_TIDCP1_SHIFT		52

#define ID_AA64MMFR1_EL1_HCX_SHIFT		40

#define ID_AA64MMFR1_EL1_AFP_SHIFT		44

#define ID_AA64MMFR1_EL1_ETS_SHIFT		36

#define ID_AA64MMFR1_EL1_TWED_SHIFT		32

#define ID_AA64MMFR1_EL1_XNX_SHIFT		28

#define ID_AA64MMFR1_EL1_SpecSEI_SHIFT		24

#define ID_AA64MMFR1_EL1_PAN_SHIFT		20

#define ID_AA64MMFR1_EL1_LO_SHIFT		16

#define ID_AA64MMFR1_EL1_HPDS_SHIFT		12

#define ID_AA64MMFR1_EL1_VH_SHIFT		8

#define ID_AA64MMFR1_EL1_VMIDBits_SHIFT		4

#define ID_AA64MMFR1_EL1_HAFDBS_SHIFT		0



#define ID_AA64MMFR1_EL1_VMIDBits_8		0

#define ID_AA64MMFR1_EL1_VMIDBits_16		2



#define ID_AA64MMFR1_EL1_TIDCP1_NI		0

#define ID_AA64MMFR1_EL1_TIDCP1_IMP		1



/* id_aa64mmfr2 */

#define ID_AA64MMFR2_EL1_E0PD_SHIFT	60

arch/arm64/kernel/cpufeature.c

+18 −18
Original line number Diff line number Diff line
@@ -362,18 +362,18 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 
};



static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TIDCP1_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0),

	ARM64_FTR_END,

};
@@ -2116,7 +2116,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.matches = has_cpuid_feature,

		.sys_reg = SYS_ID_AA64MMFR1_EL1,

		.field_pos = ID_AA64MMFR1_PAN_SHIFT,

		.field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,

		.field_width = 4,

		.sign = FTR_UNSIGNED,

		.min_field_value = 1,
@@ -2130,7 +2130,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.matches = has_cpuid_feature,

		.sys_reg = SYS_ID_AA64MMFR1_EL1,

		.field_pos = ID_AA64MMFR1_PAN_SHIFT,

		.field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,

		.field_width = 4,

		.sign = FTR_UNSIGNED,

		.min_field_value = 3,
@@ -2344,7 +2344,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.capability = ARM64_HW_DBM,

		.sys_reg = SYS_ID_AA64MMFR1_EL1,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64MMFR1_HADBS_SHIFT,

		.field_pos = ID_AA64MMFR1_EL1_HAFDBS_SHIFT,

		.field_width = 4,

		.min_field_value = 2,

		.matches = has_hw_dbm,
@@ -2614,9 +2614,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.sys_reg = SYS_ID_AA64MMFR1_EL1,

		.sign = FTR_UNSIGNED,

		.field_pos = ID_AA64MMFR1_TIDCP1_SHIFT,

		.field_pos = ID_AA64MMFR1_EL1_TIDCP1_SHIFT,

		.field_width = 4,

		.min_field_value = ID_AA64MMFR1_TIDCP1_IMP,

		.min_field_value = ID_AA64MMFR1_EL1_TIDCP1_IMP,

		.matches = has_cpuid_feature,

		.cpu_enable = cpu_trap_el0_impdef,

	},
@@ -2752,7 +2752,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),

#endif /* CONFIG_ARM64_MTE */

	HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),

	HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),

	HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),

	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),

	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),

#ifdef CONFIG_ARM64_SME

arch/arm64/kernel/hyp-stub.S

+2 −2
Original line number Diff line number Diff line
@@ -142,7 +142,7 @@ SYM_CODE_START_LOCAL(__finalise_el2) 
	msr_s	SYS_SMPRIMAP_EL2, xzr		// Make all priorities equal



	mrs	x1, id_aa64mmfr1_el1		// HCRX_EL2 present?

	ubfx	x1, x1, #ID_AA64MMFR1_HCX_SHIFT, #4

	ubfx	x1, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4

	cbz	x1, .Lskip_sme



	mrs_s	x1, SYS_HCRX_EL2
@@ -157,7 +157,7 @@ SYM_CODE_START_LOCAL(__finalise_el2) 
	tbnz	x1, #0, 1f



	// Needs to be VHE capable, obviously

	check_override id_aa64mmfr1 ID_AA64MMFR1_VHE_SHIFT 2f 1f

	check_override id_aa64mmfr1 ID_AA64MMFR1_EL1_VH_SHIFT 2f 1f



1:	mov_q	x0, HVC_STUB_ERR

	eret