Unverified Commit 8eecf1c9 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'socfpga_dts_updates_for_v5.19' of... 

Merge tag 'socfpga_dts_updates_for_v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/late

SoCFPGA dts updates for v5.19
- dtschema fix SPI NOR node
- correct dt-bindings doc for Altera gpio driver
- add support for n6000 Agilex platform and dt-bindings documentation

* tag 'socfpga_dts_updates_for_v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  arm64: dts: intel: add device tree for n6000
  dt-bindings: intel: add binding for Intel n6000
  dt-bindings: soc: add bindings for Intel HPS Copy Engine
  dt-bindings: gpio: altera: correct interrupt-cells
  ARM: dts: socfpga: align SPI NOR node name with dtschema

Link: https://lore.kernel.org/r/20220519232317.16079-1-dinguyen@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 725523dd 22511e66

Documentation/devicetree/bindings/arm/intel,socfpga.yaml

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@@ -18,6 +18,7 @@ properties: 
        items:

          - enum:

              - intel,n5x-socdk

              - intel,socfpga-agilex-n6000

              - intel,socfpga-agilex-socdk

          - const: intel,socfpga-agilex

Documentation/devicetree/bindings/gpio/gpio-altera.txt

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@@ -9,8 +9,9 @@ Required properties: 
  - The second cell is reserved and is currently unused.

- gpio-controller : Marks the device node as a GPIO controller.

- interrupt-controller: Mark the device node as an interrupt controller

- #interrupt-cells : Should be 1. The interrupt type is fixed in the hardware.

- #interrupt-cells : Should be 2. The interrupt type is fixed in the hardware.

  - The first cell is the GPIO offset number within the GPIO controller.

  - The second cell is the interrupt trigger type and level flags.

- interrupts: Specify the interrupt.

- altr,interrupt-type: Specifies the interrupt trigger type the GPIO

  hardware is synthesized. This field is required if the Altera GPIO controller
@@ -38,6 +39,6 @@ gpio_altr: gpio@ff200000 { 
	altr,interrupt-type = <IRQ_TYPE_EDGE_RISING>;

	#gpio-cells = <2>;

	gpio-controller;

	#interrupt-cells = <1>;

	#interrupt-cells = <2>;

	interrupt-controller;

};

Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

# Copyright (C) 2022, Intel Corporation

%YAML 1.2

---

$id: "http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Intel HPS Copy Engine



maintainers:

  - Matthew Gerlach <matthew.gerlach@linux.intel.com>



description: |

  The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy

  a bootable image from host memory to HPS DDR.  Additionally, there is a

  register the HPS can use to indicate the state of booting the copied image as

  well as a keep-a-live indication to the host.



properties:

  compatible:

    const: intel,hps-copy-engine



  '#dma-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    bus@80000000 {

        compatible = "simple-bus";

        reg = <0x80000000 0x60000000>,

              <0xf9000000 0x00100000>;

        reg-names = "axi_h2f", "axi_h2f_lw";

        #address-cells = <2>;

        #size-cells = <1>;

        ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;



        dma-controller@0 {

            compatible = "intel,hps-copy-engine";

            reg = <0x00000000 0x00000000 0x00001000>;

            #dma-cells = <1>;

        };

    };

arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts

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@@ -9,7 +9,7 @@ 
&qspi {

	status = "okay";



	flash0: n25q00@0 {

	flash0: flash@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "micron,mt25qu02g", "jedec,spi-nor";

arch/arm/boot/dts/socfpga_cyclone5_socdk.dts

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@@ -121,7 +121,7 @@ 
&qspi {

	status = "okay";



	flash0: n25q00@0 {

	flash0: flash@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "micron,mt25qu02g", "jedec,spi-nor";