Unverified Commit 8eb060e1 authored by Dao Lu's avatar Dao Lu Committed by Palmer Dabbelt
Browse files

arch/riscv: add Zihintpause support 



Implement support for the ZiHintPause extension.

The PAUSE instruction is a HINT that indicates the current hart’s rate
of instruction retirement should be temporarily reduced or paused.

Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Tested-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarDao Lu <daolu@rivosinc.com>
[Palmer: Some minor merge conflicts.]
Link: https://lore.kernel.org/all/20220620201530.3929352-1-daolu@rivosinc.com/
Link: https://lore.kernel.org/all/20220811053356.17375-1-palmer@rivosinc.com/


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 3aefb2ee

arch/riscv/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -60,6 +60,10 @@ riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei 
toolchain-supports-zicbom := $(call cc-option-yn, -march=$(riscv-march-y)_zicbom)

riscv-march-$(toolchain-supports-zicbom) := $(riscv-march-y)_zicbom



# Check if the toolchain supports Zihintpause extension

toolchain-supports-zihintpause := $(call cc-option-yn, -march=$(riscv-march-y)_zihintpause)

riscv-march-$(toolchain-supports-zihintpause) := $(riscv-march-y)_zihintpause



KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))

KBUILD_AFLAGS += -march=$(riscv-march-y)

arch/riscv/include/asm/hwcap.h

+5 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#ifndef _ASM_RISCV_HWCAP_H

#define _ASM_RISCV_HWCAP_H



#include <asm/errno.h>

#include <linux/bits.h>

#include <uapi/asm/hwcap.h>
@@ -55,6 +56,7 @@ enum riscv_isa_ext_id { 
	RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,

	RISCV_ISA_EXT_SVPBMT,

	RISCV_ISA_EXT_ZICBOM,

	RISCV_ISA_EXT_ZIHINTPAUSE,

	RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,

};
@@ -65,6 +67,7 @@ enum riscv_isa_ext_id { 
 */

enum riscv_isa_ext_key {

	RISCV_ISA_EXT_KEY_FPU,		/* For 'F' and 'D' */

	RISCV_ISA_EXT_KEY_ZIHINTPAUSE,

	RISCV_ISA_EXT_KEY_MAX,

};
@@ -84,6 +87,8 @@ static __always_inline int riscv_isa_ext2key(int num) 
		return RISCV_ISA_EXT_KEY_FPU;

	case RISCV_ISA_EXT_d:

		return RISCV_ISA_EXT_KEY_FPU;

	case RISCV_ISA_EXT_ZIHINTPAUSE:

		return RISCV_ISA_EXT_KEY_ZIHINTPAUSE;

	default:

		return -EINVAL;

	}

arch/riscv/include/asm/vdso/processor.h

+18 −3
Original line number Diff line number Diff line
@@ -4,15 +4,30 @@ 


#ifndef __ASSEMBLY__



#include <linux/jump_label.h>

#include <asm/barrier.h>

#include <asm/hwcap.h>



static inline void cpu_relax(void)

{

	if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) {

#ifdef __riscv_muldiv

		int dummy;

		/* In lieu of a halt instruction, induce a long-latency stall. */

		__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));

#endif

	} else {

		/*

		 * Reduce instruction retirement.

		 * This assumes the PC changes.

		 */

#ifdef __riscv_zihintpause

		__asm__ __volatile__ ("pause");

#else

		/* Encoding of the pause instruction */

		__asm__ __volatile__ (".4byte 0x100000F");

#endif

	}

	barrier();

}

arch/riscv/kernel/cpu.c

+1 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = { 
	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),

	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),

	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),

	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),

	__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),

};

arch/riscv/kernel/cpufeature.c

+1 −0
Original line number Diff line number Diff line
@@ -202,6 +202,7 @@ void __init riscv_fill_hwcap(void) 
				SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);

				SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);

				SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);

				SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);

			}

#undef SET_ISA_EXT_MAP

		}