Unverified Commit 3aefb2ee authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

riscv: implement Zicbom-based CMO instructions + the t-head variant 

This series is based on the alternatives changes done in my svpbmt
series and thus also depends on Atish's isa-extension parsing series.

It implements using the cache-management instructions from the  Zicbom-
extension to handle cache flush, etc actions on platforms needing them.

SoCs using cpu cores from T-Head like the Allwinne D1 implement a
different set of cache instructions. But while they are different,
instructions they provide the same functionality, so a variant can easly
hook into the existing alternatives mechanism on those.

[Palmer:  Some minor fixups, including a RISCV_ISA_ZICBOM dependency on
MMU that's probably not strictly necessary.  The Zicbom support will
trip up sparse for users that have new toolchains, I just sent a patch.]

Link: https://lore.kernel.org/all/20220706231536.2041855-1-heiko@sntech.de/
Link: https://lore.kernel.org/linux-sparse/20220811033138.20676-1-palmer@rivosinc.com/T/#u

* palmer/riscv-zicbom:
  riscv: implement cache-management errata for T-Head SoCs
  riscv: Add support for non-coherent devices using zicbom extension
  dt-bindings: riscv: document cbom-block-size
  of: also handle dma-noncoherent in of_dma_is_coherent()
parents 8f2f74b4 d20ec752

Documentation/devicetree/bindings/riscv/cpus.yaml

+5 −0
Original line number Diff line number Diff line
@@ -63,6 +63,11 @@ properties: 
      - riscv,sv48

      - riscv,none



  riscv,cbom-block-size:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      The blocksize in bytes for the Zicbom cache operations.



  riscv,isa:

    description:

      Identifies the specific RISC-V instruction set architecture

arch/riscv/Kconfig

+31 −0
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@ config RISCV 
	select MODULES_USE_ELF_RELA if MODULES

	select MODULE_SECTIONS if MODULES

	select OF

	select OF_DMA_DEFAULT_COHERENT

	select OF_EARLY_FLATTREE

	select OF_IRQ

	select PCI_DOMAINS_GENERIC if PCI
@@ -218,6 +219,14 @@ config PGTABLE_LEVELS 
config LOCKDEP_SUPPORT

	def_bool y



config RISCV_DMA_NONCOHERENT

	bool

	select ARCH_HAS_DMA_PREP_COHERENT

	select ARCH_HAS_SYNC_DMA_FOR_DEVICE

	select ARCH_HAS_SYNC_DMA_FOR_CPU

	select ARCH_HAS_SETUP_DMA_OPS

	select DMA_DIRECT_REMAP



source "arch/riscv/Kconfig.socs"

source "arch/riscv/Kconfig.erratas"
@@ -392,6 +401,28 @@ config RISCV_ISA_SVPBMT 


	   If you don't know what to do here, say Y.



config CC_HAS_ZICBOM

	bool

	default y if 64BIT && $(cc-option,-mabi=lp64 -march=rv64ima_zicbom)

	default y if 32BIT && $(cc-option,-mabi=ilp32 -march=rv32ima_zicbom)



config RISCV_ISA_ZICBOM

	bool "Zicbom extension support for non-coherent DMA operation"

	depends on CC_HAS_ZICBOM

	depends on !XIP_KERNEL && MMU

	select RISCV_DMA_NONCOHERENT

	select RISCV_ALTERNATIVE

	default y

	help

	   Adds support to dynamically detect the presence of the ZICBOM

	   extension (Cache Block Management Operations) and enable its

	   usage.



	   The Zicbom extension can be used to handle for example

	   non-coherent DMA support on devices that need it.



	   If you don't know what to do here, say Y.



config FPU

	bool "FPU support"

	default y

arch/riscv/Kconfig.erratas

+11 −0
Original line number Diff line number Diff line
@@ -55,4 +55,15 @@ config ERRATA_THEAD_PBMT 


	  If you don't know what to do here, say "Y".



config ERRATA_THEAD_CMO

	bool "Apply T-Head cache management errata"

	depends on ERRATA_THEAD

	select RISCV_DMA_NONCOHERENT

	default y

	help

	  This will apply the cache management errata to handle the

	  non-standard handling on non-coherent operations on T-Head SoCs.



	  If you don't know what to do here, say "Y".



endmenu # "CPU errata selection"

arch/riscv/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c 
toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei)

riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei



# Check if the toolchain supports Zicbom extension

toolchain-supports-zicbom := $(call cc-option-yn, -march=$(riscv-march-y)_zicbom)

riscv-march-$(toolchain-supports-zicbom) := $(riscv-march-y)_zicbom



KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y))

KBUILD_AFLAGS += -march=$(riscv-march-y)

arch/riscv/errata/thead/errata.c

+20 −0
Original line number Diff line number Diff line
@@ -27,6 +27,23 @@ static bool errata_probe_pbmt(unsigned int stage, 
	return false;

}



static bool errata_probe_cmo(unsigned int stage,

			     unsigned long arch_id, unsigned long impid)

{

#ifdef CONFIG_ERRATA_THEAD_CMO

	if (arch_id != 0 || impid != 0)

		return false;



	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)

		return false;



	riscv_noncoherent_supported();

	return true;

#else

	return false;

#endif

}



static u32 thead_errata_probe(unsigned int stage,

			      unsigned long archid, unsigned long impid)

{
@@ -35,6 +52,9 @@ static u32 thead_errata_probe(unsigned int stage, 
	if (errata_probe_pbmt(stage, archid, impid))

		cpu_req_errata |= (1U << ERRATA_THEAD_PBMT);



	if (errata_probe_cmo(stage, archid, impid))

		cpu_req_errata |= (1U << ERRATA_THEAD_CMO);



	return cpu_req_errata;

}