Commit 8e9f7797 authored by Michael Walle's avatar Michael Walle Committed by Shawn Guo
Browse files

arm64: dts: lx2160a: use constants in the clockgen phandle 



Now that we have constants, use them. This is just a mechanical change.

Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent b0ccb208

arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi

+57 −35
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
//

// Copyright 2018-2020 NXP



#include <dt-bindings/clock/fsl,qoriq-clockgen.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/thermal/thermal.h>
@@ -30,7 +31,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x0>;

			clocks = <&clockgen 1 0>;

			clocks = <&clockgen QORIQ_CLK_CMUX 0>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -47,7 +48,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x1>;

			clocks = <&clockgen 1 0>;

			clocks = <&clockgen QORIQ_CLK_CMUX 0>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -64,7 +65,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x100>;

			clocks = <&clockgen 1 1>;

			clocks = <&clockgen QORIQ_CLK_CMUX 1>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -81,7 +82,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x101>;

			clocks = <&clockgen 1 1>;

			clocks = <&clockgen QORIQ_CLK_CMUX 1>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -98,7 +99,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x200>;

			clocks = <&clockgen 1 2>;

			clocks = <&clockgen QORIQ_CLK_CMUX 2>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -115,7 +116,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x201>;

			clocks = <&clockgen 1 2>;

			clocks = <&clockgen QORIQ_CLK_CMUX 2>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -132,7 +133,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x300>;

			clocks = <&clockgen 1 3>;

			clocks = <&clockgen QORIQ_CLK_CMUX 3>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -149,7 +150,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x301>;

			clocks = <&clockgen 1 3>;

			clocks = <&clockgen QORIQ_CLK_CMUX 3>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -166,7 +167,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x400>;

			clocks = <&clockgen 1 4>;

			clocks = <&clockgen QORIQ_CLK_CMUX 4>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -183,7 +184,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x401>;

			clocks = <&clockgen 1 4>;

			clocks = <&clockgen QORIQ_CLK_CMUX 4>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -200,7 +201,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x500>;

			clocks = <&clockgen 1 5>;

			clocks = <&clockgen QORIQ_CLK_CMUX 5>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -217,7 +218,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x501>;

			clocks = <&clockgen 1 5>;

			clocks = <&clockgen QORIQ_CLK_CMUX 5>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -234,7 +235,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x600>;

			clocks = <&clockgen 1 6>;

			clocks = <&clockgen QORIQ_CLK_CMUX 6>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -251,7 +252,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x601>;

			clocks = <&clockgen 1 6>;

			clocks = <&clockgen QORIQ_CLK_CMUX 6>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -268,7 +269,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x700>;

			clocks = <&clockgen 1 7>;

			clocks = <&clockgen QORIQ_CLK_CMUX 7>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -285,7 +286,7 @@ 
			compatible = "arm,cortex-a72";

			enable-method = "psci";

			reg = <0x701>;

			clocks = <&clockgen 1 7>;

			clocks = <&clockgen QORIQ_CLK_CMUX 7>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;
@@ -716,7 +717,8 @@ 
			reg = <0x0 0x2000000 0x0 0x10000>;

			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "i2c";

			clocks = <&clockgen 4 15>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>;

			scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;

			status = "disabled";

		};
@@ -728,7 +730,8 @@ 
			reg = <0x0 0x2010000 0x0 0x10000>;

			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "i2c";

			clocks = <&clockgen 4 15>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>;

			status = "disabled";

		};
@@ -739,7 +742,8 @@ 
			reg = <0x0 0x2020000 0x0 0x10000>;

			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "i2c";

			clocks = <&clockgen 4 15>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>;

			status = "disabled";

		};
@@ -750,7 +754,8 @@ 
			reg = <0x0 0x2030000 0x0 0x10000>;

			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "i2c";

			clocks = <&clockgen 4 15>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>;

			status = "disabled";

		};
@@ -761,7 +766,8 @@ 
			reg = <0x0 0x2040000 0x0 0x10000>;

			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "i2c";

			clocks = <&clockgen 4 15>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>;

			scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;

			status = "disabled";

		};
@@ -773,7 +779,8 @@ 
			reg = <0x0 0x2050000 0x0 0x10000>;

			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "i2c";

			clocks = <&clockgen 4 15>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>;

			status = "disabled";

		};
@@ -784,7 +791,8 @@ 
			reg = <0x0 0x2060000 0x0 0x10000>;

			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "i2c";

			clocks = <&clockgen 4 15>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>;

			status = "disabled";

		};
@@ -795,7 +803,8 @@ 
			reg = <0x0 0x2070000 0x0 0x10000>;

			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "i2c";

			clocks = <&clockgen 4 15>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(16)>;

			status = "disabled";

		};
@@ -807,7 +816,10 @@ 
			      <0x0 0x20000000 0x0 0x10000000>;

			reg-names = "fspi_base", "fspi_mmap";

			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,

				 <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			clock-names = "fspi_en", "fspi";

			status = "disabled";

		};
@@ -818,7 +830,8 @@ 
			#size-cells = <0>;

			reg = <0x0 0x2100000 0x0 0x10000>;

			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 7>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(8)>;

			clock-names = "dspi";

			spi-num-chipselects = <5>;

			bus-num = <0>;
@@ -831,7 +844,8 @@ 
			#size-cells = <0>;

			reg = <0x0 0x2110000 0x0 0x10000>;

			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 7>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(8)>;

			clock-names = "dspi";

			spi-num-chipselects = <5>;

			bus-num = <1>;
@@ -844,7 +858,8 @@ 
			#size-cells = <0>;

			reg = <0x0 0x2120000 0x0 0x10000>;

			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 7>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(8)>;

			clock-names = "dspi";

			spi-num-chipselects = <5>;

			bus-num = <2>;
@@ -855,7 +870,8 @@ 
			compatible = "fsl,esdhc";

			reg = <0x0 0x2140000 0x0 0x10000>;

			interrupts = <0 28 0x4>; /* Level high type */

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			dma-coherent;

			voltage-ranges = <1800 1800 3300 3300>;

			sdhci,auto-cmd12;
@@ -868,7 +884,8 @@ 
			compatible = "fsl,esdhc";

			reg = <0x0 0x2150000 0x0 0x10000>;

			interrupts = <0 63 0x4>; /* Level high type */

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			dma-coherent;

			voltage-ranges = <1800 1800 3300 3300>;

			sdhci,auto-cmd12;
@@ -1004,7 +1021,8 @@ 
			      <0x7 0x100520 0x0 0x4>;

			reg-names = "ahci", "sata-ecc";

			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			dma-coherent;

			status = "disabled";

		};
@@ -1015,7 +1033,8 @@ 
			      <0x7 0x100520 0x0 0x4>;

			reg-names = "ahci", "sata-ecc";

			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			dma-coherent;

			status = "disabled";

		};
@@ -1026,7 +1045,8 @@ 
			      <0x7 0x100520 0x0 0x4>;

			reg-names = "ahci", "sata-ecc";

			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			dma-coherent;

			status = "disabled";

		};
@@ -1037,7 +1057,8 @@ 
			      <0x7 0x100520 0x0 0x4>;

			reg-names = "ahci", "sata-ecc";

			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			dma-coherent;

			status = "disabled";

		};
@@ -1310,7 +1331,8 @@ 
		ptp-timer@8b95000 {

			compatible = "fsl,dpaa2-ptp";

			reg = <0x0 0x8b95000 0x0 0x100>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			little-endian;

			fsl,extts-fifo;

		};