Commit b0ccb208 authored by Michael Walle's avatar Michael Walle Committed by Shawn Guo
Browse files

arm64: dts: ls208xa: use constants in the clockgen phandle 



Now that we have constants, use them. This is just a mechanical change.

Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent f9799323

arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

+9 −8
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
 *

 */



#include <dt-bindings/clock/fsl,qoriq-clockgen.h>

#include "fsl-ls208xa.dtsi"



&cpu {
@@ -16,7 +17,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a57";

		reg = <0x0>;

		clocks = <&clockgen 1 0>;

		clocks = <&clockgen QORIQ_CLK_CMUX 0>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster0_l2>;

		#cooling-cells = <2>;
@@ -26,7 +27,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a57";

		reg = <0x1>;

		clocks = <&clockgen 1 0>;

		clocks = <&clockgen QORIQ_CLK_CMUX 0>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster0_l2>;

		#cooling-cells = <2>;
@@ -36,7 +37,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a57";

		reg = <0x100>;

		clocks = <&clockgen 1 1>;

		clocks = <&clockgen QORIQ_CLK_CMUX 1>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster1_l2>;

		#cooling-cells = <2>;
@@ -46,7 +47,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a57";

		reg = <0x101>;

		clocks = <&clockgen 1 1>;

		clocks = <&clockgen QORIQ_CLK_CMUX 1>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster1_l2>;

		#cooling-cells = <2>;
@@ -56,7 +57,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a57";

		reg = <0x200>;

		clocks = <&clockgen 1 2>;

		clocks = <&clockgen QORIQ_CLK_CMUX 2>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster2_l2>;

		#cooling-cells = <2>;
@@ -66,7 +67,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a57";

		reg = <0x201>;

		clocks = <&clockgen 1 2>;

		clocks = <&clockgen QORIQ_CLK_CMUX 2>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster2_l2>;

		#cooling-cells = <2>;
@@ -76,7 +77,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a57";

		reg = <0x300>;

		clocks = <&clockgen 1 3>;

		clocks = <&clockgen QORIQ_CLK_CMUX 3>;

		next-level-cache = <&cluster3_l2>;

		cpu-idle-states = <&CPU_PW20>;

		#cooling-cells = <2>;
@@ -86,7 +87,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a57";

		reg = <0x301>;

		clocks = <&clockgen 1 3>;

		clocks = <&clockgen QORIQ_CLK_CMUX 3>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster3_l2>;

		#cooling-cells = <2>;

arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi

+9 −8
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
 *

 */



#include <dt-bindings/clock/fsl,qoriq-clockgen.h>

#include "fsl-ls208xa.dtsi"



&cpu {
@@ -16,7 +17,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a72";

		reg = <0x0>;

		clocks = <&clockgen 1 0>;

		clocks = <&clockgen QORIQ_CLK_CMUX 0>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster0_l2>;

		#cooling-cells = <2>;
@@ -26,7 +27,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a72";

		reg = <0x1>;

		clocks = <&clockgen 1 0>;

		clocks = <&clockgen QORIQ_CLK_CMUX 0>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster0_l2>;

		#cooling-cells = <2>;
@@ -36,7 +37,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a72";

		reg = <0x100>;

		clocks = <&clockgen 1 1>;

		clocks = <&clockgen QORIQ_CLK_CMUX 1>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster1_l2>;

		#cooling-cells = <2>;
@@ -46,7 +47,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a72";

		reg = <0x101>;

		clocks = <&clockgen 1 1>;

		clocks = <&clockgen QORIQ_CLK_CMUX 1>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster1_l2>;

		#cooling-cells = <2>;
@@ -56,7 +57,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a72";

		reg = <0x200>;

		clocks = <&clockgen 1 2>;

		clocks = <&clockgen QORIQ_CLK_CMUX 2>;

		next-level-cache = <&cluster2_l2>;

		cpu-idle-states = <&CPU_PW20>;

		#cooling-cells = <2>;
@@ -66,7 +67,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a72";

		reg = <0x201>;

		clocks = <&clockgen 1 2>;

		clocks = <&clockgen QORIQ_CLK_CMUX 2>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster2_l2>;

		#cooling-cells = <2>;
@@ -76,7 +77,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a72";

		reg = <0x300>;

		clocks = <&clockgen 1 3>;

		clocks = <&clockgen QORIQ_CLK_CMUX 3>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster3_l2>;

		#cooling-cells = <2>;
@@ -86,7 +87,7 @@ 
		device_type = "cpu";

		compatible = "arm,cortex-a72";

		reg = <0x301>;

		clocks = <&clockgen 1 3>;

		clocks = <&clockgen QORIQ_CLK_CMUX 3>;

		cpu-idle-states = <&CPU_PW20>;

		next-level-cache = <&cluster3_l2>;

		#cooling-cells = <2>;

arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi

+63 −22
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
 *

 */



#include <dt-bindings/clock/fsl,qoriq-clockgen.h>

#include <dt-bindings/thermal/thermal.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -356,84 +357,112 @@ 
		serial0: serial@21c0500 {

			compatible = "fsl,ns16550", "ns16550a";

			reg = <0x0 0x21c0500 0x0 0x100>;

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			interrupts = <0 32 0x4>; /* Level high type */

		};



		serial1: serial@21c0600 {

			compatible = "fsl,ns16550", "ns16550a";

			reg = <0x0 0x21c0600 0x0 0x100>;

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			interrupts = <0 32 0x4>; /* Level high type */

		};



		serial2: serial@21d0500 {

			compatible = "fsl,ns16550", "ns16550a";

			reg = <0x0 0x21d0500 0x0 0x100>;

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			interrupts = <0 33 0x4>; /* Level high type */

		};



		serial3: serial@21d0600 {

			compatible = "fsl,ns16550", "ns16550a";

			reg = <0x0 0x21d0600 0x0 0x100>;

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			interrupts = <0 33 0x4>; /* Level high type */

		};



		cluster1_core0_watchdog: wdt@c000000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc000000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,

				 <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster1_core1_watchdog: wdt@c010000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc010000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,

				 <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster2_core0_watchdog: wdt@c100000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc100000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,

				 <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster2_core1_watchdog: wdt@c110000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc110000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,

				 <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster3_core0_watchdog: wdt@c200000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc200000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,

				 <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster3_core1_watchdog: wdt@c210000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc210000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,

				 <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster4_core0_watchdog: wdt@c300000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc300000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,

				 <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			clock-names = "wdog_clk", "apb_pclk";

		};



		cluster4_core1_watchdog: wdt@c310000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xc310000 0x0 0x1000>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,

				 <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			clock-names = "wdog_clk", "apb_pclk";

		};
@@ -484,7 +513,8 @@ 
		ptp-timer@8b95000 {

			compatible = "fsl,dpaa2-ptp";

			reg = <0x0 0x8b95000 0x0 0x100>;

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			little-endian;

			fsl,extts-fifo;

		};
@@ -895,7 +925,8 @@ 
			#size-cells = <0>;

			reg = <0x0 0x2100000 0x0 0x10000>;

			interrupts = <0 26 0x4>; /* Level high type */

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			clock-names = "dspi";

			spi-num-chipselects = <5>;

			bus-num = <0>;
@@ -906,7 +937,8 @@ 
			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";

			reg = <0x0 0x2140000 0x0 0x10000>;

			interrupts = <0 28 0x4>; /* Level high type */

			clocks = <&clockgen 4 1>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(2)>;

			voltage-ranges = <1800 1800 3300 3300>;

			sdhci,auto-cmd12;

			little-endian;
@@ -965,7 +997,8 @@ 
			reg = <0x0 0x2000000 0x0 0x10000>;

			interrupts = <0 34 0x4>; /* Level high type */

			clock-names = "i2c";

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

		};



		i2c1: i2c@2010000 {
@@ -976,7 +1009,8 @@ 
			reg = <0x0 0x2010000 0x0 0x10000>;

			interrupts = <0 34 0x4>; /* Level high type */

			clock-names = "i2c";

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

		};



		i2c2: i2c@2020000 {
@@ -987,7 +1021,8 @@ 
			reg = <0x0 0x2020000 0x0 0x10000>;

			interrupts = <0 35 0x4>; /* Level high type */

			clock-names = "i2c";

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

		};



		i2c3: i2c@2030000 {
@@ -998,7 +1033,8 @@ 
			reg = <0x0 0x2030000 0x0 0x10000>;

			interrupts = <0 35 0x4>; /* Level high type */

			clock-names = "i2c";

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

		};



		ifc: ifc@2240000 {
@@ -1022,7 +1058,10 @@ 
			      <0x0 0x20000000 0x0 0x10000000>;

			reg-names = "QuadSPI", "QuadSPI-memory";

			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 3>, <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>,

				 <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			clock-names = "qspi_en", "qspi";

			status = "disabled";

		};
@@ -1120,7 +1159,8 @@ 
			compatible = "fsl,ls2080a-ahci";

			reg = <0x0 0x3200000 0x0 0x10000>;

			interrupts = <0 133 0x4>; /* Level high type */

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			dma-coherent;

		};
@@ -1129,7 +1169,8 @@ 
			compatible = "fsl,ls2080a-ahci";

			reg = <0x0 0x3210000 0x0 0x10000>;

			interrupts = <0 136 0x4>; /* Level high type */

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL

					    QORIQ_CLK_PLL_DIV(4)>;

			dma-coherent;

		};