Commit 8e6a2ebe authored by Joonas Lahtinen's avatar Joonas Lahtinen
Browse files

Merge tag 'topic/intel-gen-to-ver-2021-04-19' of... 

Merge tag 'topic/intel-gen-to-ver-2021-04-19' of git://anongit.freedesktop.org/drm/drm-intel into drm-intel-gt-next

Gen to ver conversions across the driver

The main change is Lucas' series [1], with Ville's GLK fixes [2] and a
cherry-pick of Matt's commit [3] from drm-intel-next as a base to avoid
conflicts.

[1] https://patchwork.freedesktop.org/series/88825/
[2] https://patchwork.freedesktop.org/series/88938/


[3] 70bfb307 ("drm/i915/display: Eliminate IS_GEN9_{BC,LP}")

Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/878s5ebny0.fsf@intel.com
parents e3bdccaf 425390c5

drivers/gpu/drm/i915/display/i9xx_plane.c

+1 −1
Original line number Diff line number Diff line
@@ -144,7 +144,7 @@ static bool i9xx_plane_has_windowing(struct intel_plane *plane) 
		return i9xx_plane == PLANE_B;

	else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))

		return false;

	else if (IS_DISPLAY_VER(dev_priv, 4))

	else if (DISPLAY_VER(dev_priv) == 4)

		return i9xx_plane == PLANE_C;

	else

		return i9xx_plane == PLANE_B ||

drivers/gpu/drm/i915/display/icl_dsi.c

+2 −2
Original line number Diff line number Diff line
@@ -592,7 +592,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 
	 * a value '0' inside TA_PARAM_REGISTERS otherwise

	 * leave all fields at HW default values.

	 */

	if (IS_DISPLAY_VER(dev_priv, 11)) {

	if (DISPLAY_VER(dev_priv) == 11) {

		if (afe_clk(encoder, crtc_state) <= 800000) {

			for_each_dsi_port(port, intel_dsi->ports) {

				tmp = intel_de_read(dev_priv,
@@ -1158,7 +1158,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 
	gen11_dsi_configure_transcoder(encoder, crtc_state);



	/* Step 4l: Gate DDI clocks */

	if (IS_DISPLAY_VER(dev_priv, 11))

	if (DISPLAY_VER(dev_priv) == 11)

		gen11_dsi_gate_clocks(encoder);

}

drivers/gpu/drm/i915/display/intel_atomic.c

+1 −1
Original line number Diff line number Diff line
@@ -332,7 +332,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta 
	    plane_state->hw.fb->format->is_yuv &&

	    plane_state->hw.fb->format->num_planes > 1) {

		struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);

		if (IS_DISPLAY_VER(dev_priv, 9)) {

		if (DISPLAY_VER(dev_priv) == 9) {

			mode = SKL_PS_SCALER_MODE_NV12;

		} else if (icl_is_hdr_plane(dev_priv, plane->id)) {

			/*

drivers/gpu/drm/i915/display/intel_audio.c

+2 −2
Original line number Diff line number Diff line
@@ -591,7 +591,7 @@ static void enable_audio_dsc_wa(struct intel_encoder *encoder, 


	val = intel_de_read(i915, AUD_CONFIG_BE);



	if (IS_DISPLAY_VER(i915, 11))

	if (DISPLAY_VER(i915) == 11)

		val |= HBLANK_EARLY_ENABLE_ICL(pipe);

	else if (DISPLAY_VER(i915) >= 12)

		val |= HBLANK_EARLY_ENABLE_TGL(pipe);
@@ -1309,7 +1309,7 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv) 
	if (DISPLAY_VER(dev_priv) >= 9) {

		aud_freq_init = intel_de_read(dev_priv, AUD_FREQ_CNTRL);



		if (INTEL_GEN(dev_priv) >= 12)

		if (DISPLAY_VER(dev_priv) >= 12)

			aud_freq = AUD_FREQ_GEN12;

		else

			aud_freq = aud_freq_init;

drivers/gpu/drm/i915/display/intel_bios.c

+5 −4
Original line number Diff line number Diff line
@@ -610,7 +610,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *i915) 
	 * Only parse SDVO mappings on gens that could have SDVO. This isn't

	 * accurate and doesn't have to be, as long as it's not too strict.

	 */

	if (!IS_DISPLAY_RANGE(i915, 3, 7)) {

	if (!IS_DISPLAY_VER(i915, 3, 7)) {

		drm_dbg_kms(&i915->drm, "Skipping SDVO device mapping\n");

		return;

	}
@@ -917,7 +917,7 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb) 
	 * Old decimal value is wake up time in multiples of 100 us.

	 */

	if (bdb->version >= 205 &&

	    (IS_GEN9_BC(i915) || DISPLAY_VER(i915) >= 10)) {

	    (DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) {

		switch (psr_table->tp1_wakeup_time) {

		case 0:

			i915->vbt.psr.tp1_wakeup_time_us = 500;
@@ -1659,7 +1659,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) 
	} else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) {

		ddc_pin_map = rkl_pch_tgp_ddc_pin_map;

		n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);

	} else if (HAS_PCH_TGP(i915) && IS_GEN9_BC(i915)) {

	} else if (HAS_PCH_TGP(i915) && DISPLAY_VER(i915) == 9) {

		ddc_pin_map = gen9bc_tgp_ddc_pin_map;

		n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map);

	} else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
@@ -2770,7 +2770,8 @@ intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915, 
	const struct intel_bios_encoder_data *devdata =

		i915->vbt.ddi_port_info[port].devdata;



	if (drm_WARN_ON_ONCE(&i915->drm, !IS_GEN9_LP(i915)))

	if (drm_WARN_ON_ONCE(&i915->drm,

			     !IS_GEMINILAKE(i915) && !IS_BROXTON(i915)))

		return false;



	return devdata && devdata->child.hpd_invert;