Commit 70bfb307 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/display: Eliminate IS_GEN9_{BC,LP} 



Now that we've eliminated INTEL_GEN(), IS_GEN_RANGE(), etc. from the
display code, we should also kill off our use of the IS_GEN9_* macros
too.  We'll do the conversion manually this time instead of using
Coccinelle since the most logical substitution can depend heavily on the
code context, and sometimes we can keep the code simpler if we make
additional adjustments such as swapping the order of if/else arms.

v2:
 - Restore a lost negation in intel_pll_is_valid().

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210407203945.1432531-1-matthew.d.roper@intel.com
parent 337d7a16

drivers/gpu/drm/i915/display/intel_bios.c

+4 −3
Original line number Diff line number Diff line
@@ -917,7 +917,7 @@ parse_psr(struct drm_i915_private *i915, const struct bdb_header *bdb) 
	 * Old decimal value is wake up time in multiples of 100 us.

	 */

	if (bdb->version >= 205 &&

	    (IS_GEN9_BC(i915) || DISPLAY_VER(i915) >= 10)) {

	    (DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) {

		switch (psr_table->tp1_wakeup_time) {

		case 0:

			i915->vbt.psr.tp1_wakeup_time_us = 500;
@@ -1659,7 +1659,7 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) 
	} else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) {

		ddc_pin_map = rkl_pch_tgp_ddc_pin_map;

		n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);

	} else if (HAS_PCH_TGP(i915) && IS_GEN9_BC(i915)) {

	} else if (HAS_PCH_TGP(i915) && IS_DISPLAY_VER(i915, 9)) {

		ddc_pin_map = gen9bc_tgp_ddc_pin_map;

		n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map);

	} else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) {
@@ -2770,7 +2770,8 @@ intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915, 
	const struct intel_bios_encoder_data *devdata =

		i915->vbt.ddi_port_info[port].devdata;



	if (drm_WARN_ON_ONCE(&i915->drm, !IS_GEN9_LP(i915)))

	if (drm_WARN_ON_ONCE(&i915->drm,

			     !IS_GEMINILAKE(i915) && !IS_BROXTON(i915)))

		return false;



	return devdata && devdata->child.hpd_invert;

drivers/gpu/drm/i915/display/intel_cdclk.c

+18 −16
Original line number Diff line number Diff line
@@ -1631,7 +1631,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
	 * Disable SSA Precharge when CD clock frequency < 500 MHz,

	 * enable otherwise.

	 */

	if (IS_GEN9_LP(dev_priv) && cdclk >= 500000)

	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&

	    cdclk >= 500000)

		val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;

	intel_de_write(dev_priv, CDCLK_CTL, val);
@@ -1732,7 +1733,8 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 
	 * Disable SSA Precharge when CD clock frequency < 500 MHz,

	 * enable otherwise.

	 */

	if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000)

	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&

	    dev_priv->cdclk.hw.cdclk >= 500000)

		expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;



	if (cdctl == expected)
@@ -1797,9 +1799,9 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 
 */

void intel_cdclk_init_hw(struct drm_i915_private *i915)

{

	if (IS_GEN9_LP(i915) || DISPLAY_VER(i915) >= 10)

	if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))

		bxt_cdclk_init_hw(i915);

	else if (IS_GEN9_BC(i915))

	else if (IS_DISPLAY_VER(i915, 9))

		skl_cdclk_init_hw(i915);

}
@@ -1812,9 +1814,9 @@ void intel_cdclk_init_hw(struct drm_i915_private *i915) 
 */

void intel_cdclk_uninit_hw(struct drm_i915_private *i915)

{

	if (DISPLAY_VER(i915) >= 10 || IS_GEN9_LP(i915))

	if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))

		bxt_cdclk_uninit_hw(i915);

	else if (IS_GEN9_BC(i915))

	else if (IS_DISPLAY_VER(i915, 9))

		skl_cdclk_uninit_hw(i915);

}
@@ -1852,7 +1854,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, 
					const struct intel_cdclk_config *b)

{

	/* Older hw doesn't have the capability */

	if (DISPLAY_VER(dev_priv) < 10 && !IS_GEN9_LP(dev_priv))

	if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv))

		return false;



	return a->cdclk != b->cdclk &&
@@ -2625,7 +2627,11 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 
			dev_priv->max_cdclk_freq = 652800;

	} else if (IS_CANNONLAKE(dev_priv)) {

		dev_priv->max_cdclk_freq = 528000;

	} else if (IS_GEN9_BC(dev_priv)) {

	} else if (IS_GEMINILAKE(dev_priv)) {

		dev_priv->max_cdclk_freq = 316800;

	} else if (IS_BROXTON(dev_priv)) {

		dev_priv->max_cdclk_freq = 624000;

	} else if (IS_DISPLAY_VER(dev_priv, 9)) {

		u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;

		int max_cdclk, vco;
@@ -2647,10 +2653,6 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 
			max_cdclk = 308571;



		dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);

	} else if (IS_GEMINILAKE(dev_priv)) {

		dev_priv->max_cdclk_freq = 316800;

	} else if (IS_BROXTON(dev_priv)) {

		dev_priv->max_cdclk_freq = 624000;

	} else if (IS_BROADWELL(dev_priv))  {

		/*

		 * FIXME with extra cooling we can allow
@@ -2878,7 +2880,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;

		dev_priv->display.calc_voltage_level = cnl_calc_voltage_level;

		dev_priv->cdclk.table = cnl_cdclk_table;

	} else if (IS_GEN9_LP(dev_priv)) {

	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {

		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;

		dev_priv->display.set_cdclk = bxt_set_cdclk;

		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
@@ -2887,7 +2889,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
			dev_priv->cdclk.table = glk_cdclk_table;

		else

			dev_priv->cdclk.table = bxt_cdclk_table;

	} else if (IS_GEN9_BC(dev_priv)) {

	} else if (IS_DISPLAY_VER(dev_priv, 9)) {

		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;

		dev_priv->display.set_cdclk = skl_set_cdclk;

		dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
@@ -2908,9 +2910,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) 
		dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;

	}



	if (DISPLAY_VER(dev_priv) >= 10 || IS_GEN9_LP(dev_priv))

	if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))

		dev_priv->display.get_cdclk = bxt_get_cdclk;

	else if (IS_GEN9_BC(dev_priv))

	else if (IS_DISPLAY_VER(dev_priv, 9))

		dev_priv->display.get_cdclk = skl_get_cdclk;

	else if (IS_BROADWELL(dev_priv))

		dev_priv->display.get_cdclk = bdw_get_cdclk;

drivers/gpu/drm/i915/display/intel_csr.c

+1 −1
Original line number Diff line number Diff line
@@ -284,7 +284,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) 


	mask = DC_STATE_DEBUG_MASK_MEMORY_UP;



	if (IS_GEN9_LP(dev_priv))

	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))

		mask |= DC_STATE_DEBUG_MASK_CORES;



	/* The below bit doesn't need to be cleared ever afterwards */

drivers/gpu/drm/i915/display/intel_ddi.c

+20 −17
Original line number Diff line number Diff line
@@ -113,7 +113,8 @@ void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, 
							      &n_entries);



	/* If we're boosting the current, set bit 31 of trans1 */

	if (IS_GEN9_BC(dev_priv) && intel_bios_encoder_dp_boost_level(encoder->devdata))

	if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv) &&

	    intel_bios_encoder_dp_boost_level(encoder->devdata))

		iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;



	for (i = 0; i < n_entries; i++) {
@@ -146,7 +147,8 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, 
		level = n_entries - 1;



	/* If we're boosting the current, set bit 31 of trans1 */

	if (IS_GEN9_BC(dev_priv) && intel_bios_encoder_hdmi_boost_level(encoder->devdata))

	if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv) &&

	    intel_bios_encoder_hdmi_boost_level(encoder->devdata))

		iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;



	/* Entry 9 is for HDMI: */
@@ -759,7 +761,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 
		*is_dp_mst = mst_pipe_mask;



out:

	if (*pipe_mask && IS_GEN9_LP(dev_priv)) {

	if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) {

		tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));

		if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |

			    BXT_PHY_LANE_POWERDOWN_ACK |
@@ -987,7 +989,7 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, 
			icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);

	} else if (IS_CANNONLAKE(dev_priv)) {

		cnl_get_buf_trans(encoder, crtc_state, &n_entries);

	} else if (IS_GEN9_LP(dev_priv)) {

	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {

		bxt_get_buf_trans(encoder, crtc_state, &n_entries);

	} else {

		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
@@ -1555,7 +1557,7 @@ hsw_set_signal_levels(struct intel_dp *intel_dp, 
	intel_dp->DP &= ~DDI_BUF_EMP_MASK;

	intel_dp->DP |= signal_levels;



	if (IS_GEN9_BC(dev_priv))

	if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv))

		skl_ddi_set_iboost(encoder, crtc_state, level);



	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
@@ -2648,7 +2650,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, 
		icl_ddi_vswing_sequence(encoder, crtc_state, level);

	else if (IS_CANNONLAKE(dev_priv))

		cnl_ddi_vswing_sequence(encoder, crtc_state, level);

	else if (IS_GEN9_LP(dev_priv))

	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))

		bxt_ddi_vswing_sequence(encoder, crtc_state, level);

	else

		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
@@ -3096,16 +3098,16 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 
		icl_ddi_vswing_sequence(encoder, crtc_state, level);

	else if (IS_CANNONLAKE(dev_priv))

		cnl_ddi_vswing_sequence(encoder, crtc_state, level);

	else if (IS_GEN9_LP(dev_priv))

	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))

		bxt_ddi_vswing_sequence(encoder, crtc_state, level);

	else

		intel_prepare_hdmi_ddi_buffers(encoder, level);



	if (IS_GEN9_BC(dev_priv))

	if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv))

		skl_ddi_set_iboost(encoder, crtc_state, level);



	/* Display WA #1143: skl,kbl,cfl */

	if (IS_GEN9_BC(dev_priv)) {

	if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) {

		/*

		 * For some reason these chicken bits have been

		 * stuffed into a transcoder register, event though
@@ -3321,7 +3323,7 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 
		 * Type-C ports.  Skip this step for TBT.

		 */

		intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);

	else if (IS_GEN9_LP(dev_priv))

	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))

		bxt_ddi_phy_set_lane_optim_mask(encoder,

						crtc_state->lane_lat_optim_mask);

}
@@ -3679,7 +3681,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, 
	if (!pipe_config->bigjoiner_slave)

		ddi_dotclock_get(pipe_config);



	if (IS_GEN9_LP(dev_priv))

	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))

		pipe_config->lane_lat_optim_mask =

			bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
@@ -3885,7 +3887,7 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder, 
			pipe_config->pch_pfit.enabled ||

			pipe_config->crc_enabled;



	if (IS_GEN9_LP(dev_priv))

	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))

		pipe_config->lane_lat_optim_mask =

			bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
@@ -4053,7 +4055,7 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 
		dig_port->dp.set_signal_levels = icl_set_signal_levels;

	else if (IS_CANNONLAKE(dev_priv))

		dig_port->dp.set_signal_levels = cnl_set_signal_levels;

	else if (IS_GEN9_LP(dev_priv))

	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))

		dig_port->dp.set_signal_levels = bxt_set_signal_levels;

	else

		dig_port->dp.set_signal_levels = hsw_set_signal_levels;
@@ -4296,7 +4298,7 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) 
	/* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only

	 *                     supported configuration

	 */

	if (IS_GEN9_LP(dev_priv))

	if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))

		return true;



	/* Cannonlake: Most of SKUs don't support DDI_E, and the only
@@ -4585,10 +4587,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 
		encoder->disable_clock = cnl_ddi_disable_clock;

		encoder->is_clock_enabled = cnl_ddi_is_clock_enabled;

		encoder->get_config = cnl_ddi_get_config;

	} else if (IS_GEN9_LP(dev_priv)) {

	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {

		/* BXT/GLK have fixed PLL->port mapping */

		encoder->get_config = bxt_ddi_get_config;

	} else if (IS_GEN9_BC(dev_priv)) {

	} else if (IS_DISPLAY_VER(dev_priv, 9)) {

		encoder->enable_clock = skl_ddi_enable_clock;

		encoder->disable_clock = skl_ddi_disable_clock;

		encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
@@ -4672,7 +4674,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) 
		else

			dig_port->connected = lpt_digital_port_connected;

	} else if (DISPLAY_VER(dev_priv) >= 8) {

		if (port == PORT_A || IS_GEN9_LP(dev_priv))

		if (port == PORT_A || IS_GEMINILAKE(dev_priv) ||

		    IS_BROXTON(dev_priv))

			dig_port->connected = bdw_digital_port_connected;

		else

			dig_port->connected = lpt_digital_port_connected;

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

+4 −4
Original line number Diff line number Diff line
@@ -881,7 +881,7 @@ intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	if (IS_GEN9_BC(dev_priv)) {

	if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) {

		const struct ddi_buf_trans *ddi_translations =

			skl_get_buf_trans_edp(encoder, n_entries);

		*n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
@@ -919,7 +919,7 @@ intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	if (IS_GEN9_BC(dev_priv)) {

	if (IS_DISPLAY_VER(dev_priv, 9) && !IS_BROXTON(dev_priv)) {

		return skl_get_buf_trans_hdmi(dev_priv, n_entries);

	} else if (IS_BROADWELL(dev_priv)) {

		*n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
@@ -1370,10 +1370,10 @@ int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder, 
	} else if (IS_CANNONLAKE(dev_priv)) {

		cnl_get_buf_trans_hdmi(encoder, &n_entries);

		*default_entry = n_entries - 1;

	} else if (IS_GEN9_LP(dev_priv)) {

	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {

		bxt_get_buf_trans_hdmi(encoder, &n_entries);

		*default_entry = n_entries - 1;

	} else if (IS_GEN9_BC(dev_priv)) {

	} else if (IS_DISPLAY_VER(dev_priv, 9)) {

		intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);

		*default_entry = 8;

	} else if (IS_BROADWELL(dev_priv)) {